Commit 9cbc6348 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'staging-5.4-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging

Pull staging/IIO driver fixes from Greg KH:
 "Here are some staging and IIO driver fixes for 5.4-rc3.

  The "biggest" thing here is a removal of the fbtft device and flexfb
  code as they have been abandoned by their authors and are no longer
  needed for that hardware.

  Other than that, the usual amount of staging driver and iio driver
  fixes for reported issues, and some speakup sysfs file documentation,
  which has been long awaited for.

  All have been in linux-next with no reported issues"

* tag 'staging-5.4-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (32 commits)
  iio: Fix an undefied reference error in noa1305_probe
  iio: light: opt3001: fix mutex unlock race
  iio: adc: ad799x: fix probe error handling
  iio: light: add missing vcnl4040 of_compatible
  iio: light: fix vcnl4000 devicetree hooks
  iio: imu: st_lsm6dsx: fix waitime for st_lsm6dsx i2c controller
  iio: adc: axp288: Override TS pin bias current for some models
  iio: imu: adis16400: fix memory leak
  iio: imu: adis16400: release allocated memory on failure
  iio: adc: stm32-adc: fix a race when using several adcs with dma and irq
  iio: adc: stm32-adc: move registers definitions
  iio: accel: adxl372: Perform a reset at start up
  iio: accel: adxl372: Fix push to buffers lost samples
  iio: accel: adxl372: Fix/remove limitation for FIFO samples
  iio: adc: hx711: fix bug in sampling of data
  staging: vt6655: Fix memory leak in vt6655_probe
  staging: exfat: Use kvzalloc() instead of kzalloc() for exfat_sb_info
  Staging: fbtft: fix memory leak in fbtft_framebuffer_alloc
  staging: speakup: document sysfs attributes
  staging: rtl8188eu: fix HighestRate check in odm_ARFBRefresh_8188E()
  ...
parents 82c87e7d 3f3d3162
...@@ -474,12 +474,17 @@ static int adxl372_configure_fifo(struct adxl372_state *st) ...@@ -474,12 +474,17 @@ static int adxl372_configure_fifo(struct adxl372_state *st)
if (ret < 0) if (ret < 0)
return ret; return ret;
fifo_samples = st->watermark & 0xFF; /*
* watermark stores the number of sets; we need to write the FIFO
* registers with the number of samples
*/
fifo_samples = (st->watermark * st->fifo_set_size);
fifo_ctl = ADXL372_FIFO_CTL_FORMAT_MODE(st->fifo_format) | fifo_ctl = ADXL372_FIFO_CTL_FORMAT_MODE(st->fifo_format) |
ADXL372_FIFO_CTL_MODE_MODE(st->fifo_mode) | ADXL372_FIFO_CTL_MODE_MODE(st->fifo_mode) |
ADXL372_FIFO_CTL_SAMPLES_MODE(st->watermark); ADXL372_FIFO_CTL_SAMPLES_MODE(fifo_samples);
ret = regmap_write(st->regmap, ADXL372_FIFO_SAMPLES, fifo_samples); ret = regmap_write(st->regmap,
ADXL372_FIFO_SAMPLES, fifo_samples & 0xFF);
if (ret < 0) if (ret < 0)
return ret; return ret;
...@@ -548,8 +553,7 @@ static irqreturn_t adxl372_trigger_handler(int irq, void *p) ...@@ -548,8 +553,7 @@ static irqreturn_t adxl372_trigger_handler(int irq, void *p)
goto err; goto err;
/* Each sample is 2 bytes */ /* Each sample is 2 bytes */
for (i = 0; i < fifo_entries * sizeof(u16); for (i = 0; i < fifo_entries; i += st->fifo_set_size)
i += st->fifo_set_size * sizeof(u16))
iio_push_to_buffers(indio_dev, &st->fifo_buf[i]); iio_push_to_buffers(indio_dev, &st->fifo_buf[i]);
} }
err: err:
...@@ -571,6 +575,14 @@ static int adxl372_setup(struct adxl372_state *st) ...@@ -571,6 +575,14 @@ static int adxl372_setup(struct adxl372_state *st)
return -ENODEV; return -ENODEV;
} }
/*
* Perform a software reset to make sure the device is in a consistent
* state after start up.
*/
ret = regmap_write(st->regmap, ADXL372_RESET, ADXL372_RESET_CODE);
if (ret < 0)
return ret;
ret = adxl372_set_op_mode(st, ADXL372_STANDBY); ret = adxl372_set_op_mode(st, ADXL372_STANDBY);
if (ret < 0) if (ret < 0)
return ret; return ret;
......
...@@ -117,7 +117,7 @@ ...@@ -117,7 +117,7 @@
#define BMC150_ACCEL_SLEEP_1_SEC 0x0F #define BMC150_ACCEL_SLEEP_1_SEC 0x0F
#define BMC150_ACCEL_REG_TEMP 0x08 #define BMC150_ACCEL_REG_TEMP 0x08
#define BMC150_ACCEL_TEMP_CENTER_VAL 24 #define BMC150_ACCEL_TEMP_CENTER_VAL 23
#define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2)) #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
#define BMC150_AUTO_SUSPEND_DELAY_MS 2000 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000
......
...@@ -810,10 +810,10 @@ static int ad799x_probe(struct i2c_client *client, ...@@ -810,10 +810,10 @@ static int ad799x_probe(struct i2c_client *client,
ret = ad799x_write_config(st, st->chip_config->default_config); ret = ad799x_write_config(st, st->chip_config->default_config);
if (ret < 0) if (ret < 0)
goto error_disable_reg; goto error_disable_vref;
ret = ad799x_read_config(st); ret = ad799x_read_config(st);
if (ret < 0) if (ret < 0)
goto error_disable_reg; goto error_disable_vref;
st->config = ret; st->config = ret;
ret = iio_triggered_buffer_setup(indio_dev, NULL, ret = iio_triggered_buffer_setup(indio_dev, NULL,
......
...@@ -7,6 +7,7 @@ ...@@ -7,6 +7,7 @@
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*/ */
#include <linux/dmi.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/device.h> #include <linux/device.h>
...@@ -25,6 +26,11 @@ ...@@ -25,6 +26,11 @@
#define AXP288_ADC_EN_MASK 0xF0 #define AXP288_ADC_EN_MASK 0xF0
#define AXP288_ADC_TS_ENABLE 0x01 #define AXP288_ADC_TS_ENABLE 0x01
#define AXP288_ADC_TS_BIAS_MASK GENMASK(5, 4)
#define AXP288_ADC_TS_BIAS_20UA (0 << 4)
#define AXP288_ADC_TS_BIAS_40UA (1 << 4)
#define AXP288_ADC_TS_BIAS_60UA (2 << 4)
#define AXP288_ADC_TS_BIAS_80UA (3 << 4)
#define AXP288_ADC_TS_CURRENT_ON_OFF_MASK GENMASK(1, 0) #define AXP288_ADC_TS_CURRENT_ON_OFF_MASK GENMASK(1, 0)
#define AXP288_ADC_TS_CURRENT_OFF (0 << 0) #define AXP288_ADC_TS_CURRENT_OFF (0 << 0)
#define AXP288_ADC_TS_CURRENT_ON_WHEN_CHARGING (1 << 0) #define AXP288_ADC_TS_CURRENT_ON_WHEN_CHARGING (1 << 0)
...@@ -177,10 +183,36 @@ static int axp288_adc_read_raw(struct iio_dev *indio_dev, ...@@ -177,10 +183,36 @@ static int axp288_adc_read_raw(struct iio_dev *indio_dev,
return ret; return ret;
} }
/*
* We rely on the machine's firmware to correctly setup the TS pin bias current
* at boot. This lists systems with broken fw where we need to set it ourselves.
*/
static const struct dmi_system_id axp288_adc_ts_bias_override[] = {
{
/* Lenovo Ideapad 100S (11 inch) */
.matches = {
DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"),
DMI_MATCH(DMI_PRODUCT_VERSION, "Lenovo ideapad 100S-11IBY"),
},
.driver_data = (void *)(uintptr_t)AXP288_ADC_TS_BIAS_80UA,
},
{}
};
static int axp288_adc_initialize(struct axp288_adc_info *info) static int axp288_adc_initialize(struct axp288_adc_info *info)
{ {
const struct dmi_system_id *bias_override;
int ret, adc_enable_val; int ret, adc_enable_val;
bias_override = dmi_first_match(axp288_adc_ts_bias_override);
if (bias_override) {
ret = regmap_update_bits(info->regmap, AXP288_ADC_TS_PIN_CTRL,
AXP288_ADC_TS_BIAS_MASK,
(uintptr_t)bias_override->driver_data);
if (ret)
return ret;
}
/* /*
* Determine if the TS pin is enabled and set the TS current-source * Determine if the TS pin is enabled and set the TS current-source
* accordingly. * accordingly.
......
...@@ -100,14 +100,14 @@ struct hx711_data { ...@@ -100,14 +100,14 @@ struct hx711_data {
static int hx711_cycle(struct hx711_data *hx711_data) static int hx711_cycle(struct hx711_data *hx711_data)
{ {
int val; unsigned long flags;
/* /*
* if preempted for more then 60us while PD_SCK is high: * if preempted for more then 60us while PD_SCK is high:
* hx711 is going in reset * hx711 is going in reset
* ==> measuring is false * ==> measuring is false
*/ */
preempt_disable(); local_irq_save(flags);
gpiod_set_value(hx711_data->gpiod_pd_sck, 1); gpiod_set_value(hx711_data->gpiod_pd_sck, 1);
/* /*
...@@ -117,7 +117,6 @@ static int hx711_cycle(struct hx711_data *hx711_data) ...@@ -117,7 +117,6 @@ static int hx711_cycle(struct hx711_data *hx711_data)
*/ */
ndelay(hx711_data->data_ready_delay_ns); ndelay(hx711_data->data_ready_delay_ns);
val = gpiod_get_value(hx711_data->gpiod_dout);
/* /*
* here we are not waiting for 0.2 us as suggested by the datasheet, * here we are not waiting for 0.2 us as suggested by the datasheet,
* because the oscilloscope showed in a test scenario * because the oscilloscope showed in a test scenario
...@@ -125,7 +124,7 @@ static int hx711_cycle(struct hx711_data *hx711_data) ...@@ -125,7 +124,7 @@ static int hx711_cycle(struct hx711_data *hx711_data)
* and 0.56 us for PD_SCK low on TI Sitara with 800 MHz * and 0.56 us for PD_SCK low on TI Sitara with 800 MHz
*/ */
gpiod_set_value(hx711_data->gpiod_pd_sck, 0); gpiod_set_value(hx711_data->gpiod_pd_sck, 0);
preempt_enable(); local_irq_restore(flags);
/* /*
* make it a square wave for addressing cases with capacitance on * make it a square wave for addressing cases with capacitance on
...@@ -133,7 +132,8 @@ static int hx711_cycle(struct hx711_data *hx711_data) ...@@ -133,7 +132,8 @@ static int hx711_cycle(struct hx711_data *hx711_data)
*/ */
ndelay(hx711_data->data_ready_delay_ns); ndelay(hx711_data->data_ready_delay_ns);
return val; /* sample as late as possible */
return gpiod_get_value(hx711_data->gpiod_dout);
} }
static int hx711_read(struct hx711_data *hx711_data) static int hx711_read(struct hx711_data *hx711_data)
......
...@@ -1219,6 +1219,11 @@ static int meson_sar_adc_probe(struct platform_device *pdev) ...@@ -1219,6 +1219,11 @@ static int meson_sar_adc_probe(struct platform_device *pdev)
if (IS_ERR(base)) if (IS_ERR(base))
return PTR_ERR(base); return PTR_ERR(base);
priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
priv->param->regmap_config);
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
irq = irq_of_parse_and_map(pdev->dev.of_node, 0); irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
if (!irq) if (!irq)
return -EINVAL; return -EINVAL;
...@@ -1228,11 +1233,6 @@ static int meson_sar_adc_probe(struct platform_device *pdev) ...@@ -1228,11 +1233,6 @@ static int meson_sar_adc_probe(struct platform_device *pdev)
if (ret) if (ret)
return ret; return ret;
priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
priv->param->regmap_config);
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
priv->clkin = devm_clk_get(&pdev->dev, "clkin"); priv->clkin = devm_clk_get(&pdev->dev, "clkin");
if (IS_ERR(priv->clkin)) { if (IS_ERR(priv->clkin)) {
dev_err(&pdev->dev, "failed to get clkin\n"); dev_err(&pdev->dev, "failed to get clkin\n");
......
...@@ -24,33 +24,6 @@ ...@@ -24,33 +24,6 @@
#include "stm32-adc-core.h" #include "stm32-adc-core.h"
/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
/* STM32F4_ADC_CSR - bit fields */
#define STM32F4_EOC3 BIT(17)
#define STM32F4_EOC2 BIT(9)
#define STM32F4_EOC1 BIT(1)
/* STM32F4_ADC_CCR - bit fields */
#define STM32F4_ADC_ADCPRE_SHIFT 16
#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
/* STM32H7 - common registers for all ADC instances */
#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
/* STM32H7_ADC_CSR - bit fields */
#define STM32H7_EOC_SLV BIT(18)
#define STM32H7_EOC_MST BIT(2)
/* STM32H7_ADC_CCR - bit fields */
#define STM32H7_PRESC_SHIFT 18
#define STM32H7_PRESC_MASK GENMASK(21, 18)
#define STM32H7_CKMODE_SHIFT 16
#define STM32H7_CKMODE_MASK GENMASK(17, 16)
#define STM32_ADC_CORE_SLEEP_DELAY_MS 2000 #define STM32_ADC_CORE_SLEEP_DELAY_MS 2000
/* SYSCFG registers */ /* SYSCFG registers */
...@@ -71,6 +44,8 @@ ...@@ -71,6 +44,8 @@
* @eoc1: adc1 end of conversion flag in @csr * @eoc1: adc1 end of conversion flag in @csr
* @eoc2: adc2 end of conversion flag in @csr * @eoc2: adc2 end of conversion flag in @csr
* @eoc3: adc3 end of conversion flag in @csr * @eoc3: adc3 end of conversion flag in @csr
* @ier: interrupt enable register offset for each adc
* @eocie_msk: end of conversion interrupt enable mask in @ier
*/ */
struct stm32_adc_common_regs { struct stm32_adc_common_regs {
u32 csr; u32 csr;
...@@ -78,6 +53,8 @@ struct stm32_adc_common_regs { ...@@ -78,6 +53,8 @@ struct stm32_adc_common_regs {
u32 eoc1_msk; u32 eoc1_msk;
u32 eoc2_msk; u32 eoc2_msk;
u32 eoc3_msk; u32 eoc3_msk;
u32 ier;
u32 eocie_msk;
}; };
struct stm32_adc_priv; struct stm32_adc_priv;
...@@ -303,6 +280,8 @@ static const struct stm32_adc_common_regs stm32f4_adc_common_regs = { ...@@ -303,6 +280,8 @@ static const struct stm32_adc_common_regs stm32f4_adc_common_regs = {
.eoc1_msk = STM32F4_EOC1, .eoc1_msk = STM32F4_EOC1,
.eoc2_msk = STM32F4_EOC2, .eoc2_msk = STM32F4_EOC2,
.eoc3_msk = STM32F4_EOC3, .eoc3_msk = STM32F4_EOC3,
.ier = STM32F4_ADC_CR1,
.eocie_msk = STM32F4_EOCIE,
}; };
/* STM32H7 common registers definitions */ /* STM32H7 common registers definitions */
...@@ -311,8 +290,24 @@ static const struct stm32_adc_common_regs stm32h7_adc_common_regs = { ...@@ -311,8 +290,24 @@ static const struct stm32_adc_common_regs stm32h7_adc_common_regs = {
.ccr = STM32H7_ADC_CCR, .ccr = STM32H7_ADC_CCR,
.eoc1_msk = STM32H7_EOC_MST, .eoc1_msk = STM32H7_EOC_MST,
.eoc2_msk = STM32H7_EOC_SLV, .eoc2_msk = STM32H7_EOC_SLV,
.ier = STM32H7_ADC_IER,
.eocie_msk = STM32H7_EOCIE,
};
static const unsigned int stm32_adc_offset[STM32_ADC_MAX_ADCS] = {
0, STM32_ADC_OFFSET, STM32_ADC_OFFSET * 2,
}; };
static unsigned int stm32_adc_eoc_enabled(struct stm32_adc_priv *priv,
unsigned int adc)
{
u32 ier, offset = stm32_adc_offset[adc];
ier = readl_relaxed(priv->common.base + offset + priv->cfg->regs->ier);
return ier & priv->cfg->regs->eocie_msk;
}
/* ADC common interrupt for all instances */ /* ADC common interrupt for all instances */
static void stm32_adc_irq_handler(struct irq_desc *desc) static void stm32_adc_irq_handler(struct irq_desc *desc)
{ {
...@@ -323,13 +318,28 @@ static void stm32_adc_irq_handler(struct irq_desc *desc) ...@@ -323,13 +318,28 @@ static void stm32_adc_irq_handler(struct irq_desc *desc)
chained_irq_enter(chip, desc); chained_irq_enter(chip, desc);
status = readl_relaxed(priv->common.base + priv->cfg->regs->csr); status = readl_relaxed(priv->common.base + priv->cfg->regs->csr);
if (status & priv->cfg->regs->eoc1_msk) /*
* End of conversion may be handled by using IRQ or DMA. There may be a
* race here when two conversions complete at the same time on several
* ADCs. EOC may be read 'set' for several ADCs, with:
* - an ADC configured to use DMA (EOC triggers the DMA request, and
* is then automatically cleared by DR read in hardware)
* - an ADC configured to use IRQs (EOCIE bit is set. The handler must
* be called in this case)
* So both EOC status bit in CSR and EOCIE control bit must be checked
* before invoking the interrupt handler (e.g. call ISR only for
* IRQ-enabled ADCs).
*/
if (status & priv->cfg->regs->eoc1_msk &&
stm32_adc_eoc_enabled(priv, 0))
generic_handle_irq(irq_find_mapping(priv->domain, 0)); generic_handle_irq(irq_find_mapping(priv->domain, 0));
if (status & priv->cfg->regs->eoc2_msk) if (status & priv->cfg->regs->eoc2_msk &&
stm32_adc_eoc_enabled(priv, 1))
generic_handle_irq(irq_find_mapping(priv->domain, 1)); generic_handle_irq(irq_find_mapping(priv->domain, 1));
if (status & priv->cfg->regs->eoc3_msk) if (status & priv->cfg->regs->eoc3_msk &&
stm32_adc_eoc_enabled(priv, 2))
generic_handle_irq(irq_find_mapping(priv->domain, 2)); generic_handle_irq(irq_find_mapping(priv->domain, 2));
chained_irq_exit(chip, desc); chained_irq_exit(chip, desc);
......
...@@ -25,8 +25,145 @@ ...@@ -25,8 +25,145 @@
* -------------------------------------------------------- * --------------------------------------------------------
*/ */
#define STM32_ADC_MAX_ADCS 3 #define STM32_ADC_MAX_ADCS 3
#define STM32_ADC_OFFSET 0x100
#define STM32_ADCX_COMN_OFFSET 0x300 #define STM32_ADCX_COMN_OFFSET 0x300
/* STM32F4 - Registers for each ADC instance */
#define STM32F4_ADC_SR 0x00
#define STM32F4_ADC_CR1 0x04
#define STM32F4_ADC_CR2 0x08
#define STM32F4_ADC_SMPR1 0x0C
#define STM32F4_ADC_SMPR2 0x10
#define STM32F4_ADC_HTR 0x24
#define STM32F4_ADC_LTR 0x28
#define STM32F4_ADC_SQR1 0x2C
#define STM32F4_ADC_SQR2 0x30
#define STM32F4_ADC_SQR3 0x34
#define STM32F4_ADC_JSQR 0x38
#define STM32F4_ADC_JDR1 0x3C
#define STM32F4_ADC_JDR2 0x40
#define STM32F4_ADC_JDR3 0x44
#define STM32F4_ADC_JDR4 0x48
#define STM32F4_ADC_DR 0x4C
/* STM32F4 - common registers for all ADC instances: 1, 2 & 3 */
#define STM32F4_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
#define STM32F4_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x04)
/* STM32F4_ADC_SR - bit fields */
#define STM32F4_STRT BIT(4)
#define STM32F4_EOC BIT(1)
/* STM32F4_ADC_CR1 - bit fields */
#define STM32F4_RES_SHIFT 24
#define STM32F4_RES_MASK GENMASK(25, 24)
#define STM32F4_SCAN BIT(8)
#define STM32F4_EOCIE BIT(5)
/* STM32F4_ADC_CR2 - bit fields */
#define STM32F4_SWSTART BIT(30)
#define STM32F4_EXTEN_SHIFT 28
#define STM32F4_EXTEN_MASK GENMASK(29, 28)
#define STM32F4_EXTSEL_SHIFT 24
#define STM32F4_EXTSEL_MASK GENMASK(27, 24)
#define STM32F4_EOCS BIT(10)
#define STM32F4_DDS BIT(9)
#define STM32F4_DMA BIT(8)
#define STM32F4_ADON BIT(0)
/* STM32F4_ADC_CSR - bit fields */
#define STM32F4_EOC3 BIT(17)
#define STM32F4_EOC2 BIT(9)
#define STM32F4_EOC1 BIT(1)
/* STM32F4_ADC_CCR - bit fields */
#define STM32F4_ADC_ADCPRE_SHIFT 16
#define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
/* STM32H7 - Registers for each ADC instance */
#define STM32H7_ADC_ISR 0x00
#define STM32H7_ADC_IER 0x04
#define STM32H7_ADC_CR 0x08
#define STM32H7_ADC_CFGR 0x0C
#define STM32H7_ADC_SMPR1 0x14
#define STM32H7_ADC_SMPR2 0x18
#define STM32H7_ADC_PCSEL 0x1C
#define STM32H7_ADC_SQR1 0x30
#define STM32H7_ADC_SQR2 0x34
#define STM32H7_ADC_SQR3 0x38
#define STM32H7_ADC_SQR4 0x3C
#define STM32H7_ADC_DR 0x40
#define STM32H7_ADC_DIFSEL 0xC0
#define STM32H7_ADC_CALFACT 0xC4
#define STM32H7_ADC_CALFACT2 0xC8
/* STM32H7 - common registers for all ADC instances */
#define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
#define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
/* STM32H7_ADC_ISR - bit fields */
#define STM32MP1_VREGREADY BIT(12)
#define STM32H7_EOC BIT(2)
#define STM32H7_ADRDY BIT(0)
/* STM32H7_ADC_IER - bit fields */
#define STM32H7_EOCIE STM32H7_EOC
/* STM32H7_ADC_CR - bit fields */
#define STM32H7_ADCAL BIT(31)
#define STM32H7_ADCALDIF BIT(30)
#define STM32H7_DEEPPWD BIT(29)
#define STM32H7_ADVREGEN BIT(28)
#define STM32H7_LINCALRDYW6 BIT(27)
#define STM32H7_LINCALRDYW5 BIT(26)
#define STM32H7_LINCALRDYW4 BIT(25)
#define STM32H7_LINCALRDYW3 BIT(24)
#define STM32H7_LINCALRDYW2 BIT(23)
#define STM32H7_LINCALRDYW1 BIT(22)
#define STM32H7_ADCALLIN BIT(16)
#define STM32H7_BOOST BIT(8)
#define STM32H7_ADSTP BIT(4)
#define STM32H7_ADSTART BIT(2)
#define STM32H7_ADDIS BIT(1)
#define STM32H7_ADEN BIT(0)
/* STM32H7_ADC_CFGR bit fields */
#define STM32H7_EXTEN_SHIFT 10
#define STM32H7_EXTEN_MASK GENMASK(11, 10)
#define STM32H7_EXTSEL_SHIFT 5
#define STM32H7_EXTSEL_MASK GENMASK(9, 5)
#define STM32H7_RES_SHIFT 2
#define STM32H7_RES_MASK GENMASK(4, 2)
#define STM32H7_DMNGT_SHIFT 0
#define STM32H7_DMNGT_MASK GENMASK(1, 0)
enum stm32h7_adc_dmngt {
STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */
STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */
STM32H7_DMNGT_DFSDM, /* DFSDM mode */
STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */
};
/* STM32H7_ADC_CALFACT - bit fields */
#define STM32H7_CALFACT_D_SHIFT 16
#define STM32H7_CALFACT_D_MASK GENMASK(26, 16)
#define STM32H7_CALFACT_S_SHIFT 0
#define STM32H7_CALFACT_S_MASK GENMASK(10, 0)
/* STM32H7_ADC_CALFACT2 - bit fields */
#define STM32H7_LINCALFACT_SHIFT 0
#define STM32H7_LINCALFACT_MASK GENMASK(29, 0)
/* STM32H7_ADC_CSR - bit fields */
#define STM32H7_EOC_SLV BIT(18)
#define STM32H7_EOC_MST BIT(2)
/* STM32H7_ADC_CCR - bit fields */
#define STM32H7_PRESC_SHIFT 18
#define STM32H7_PRESC_MASK GENMASK(21, 18)
#define STM32H7_CKMODE_SHIFT 16
#define STM32H7_CKMODE_MASK GENMASK(17, 16)
/** /**
* struct stm32_adc_common - stm32 ADC driver common data (for all instances) * struct stm32_adc_common - stm32 ADC driver common data (for all instances)
* @base: control registers base cpu addr * @base: control registers base cpu addr
......
...@@ -28,115 +28,6 @@ ...@@ -28,115 +28,6 @@
#include "stm32-adc-core.h" #include "stm32-adc-core.h"
/* STM32F4 - Registers for each ADC instance */
#define STM32F4_ADC_SR 0x00
#define STM32F4_ADC_CR1 0x04
#define STM32F4_ADC_CR2 0x08
#define STM32F4_ADC_SMPR1 0x0C
#define STM32F4_ADC_SMPR2 0x10
#define STM32F4_ADC_HTR 0x24
#define STM32F4_ADC_LTR 0x28
#define STM32F4_ADC_SQR1 0x2C
#define STM32F4_ADC_SQR2 0x30
#define STM32F4_ADC_SQR3 0x34
#define STM32F4_ADC_JSQR 0x38
#define STM32F4_ADC_JDR1 0x3C
#define STM32F4_ADC_JDR2 0x40
#define STM32F4_ADC_JDR3 0x44
#define STM32F4_ADC_JDR4 0x48
#define STM32F4_ADC_DR 0x4C
/* STM32F4_ADC_SR - bit fields */
#define STM32F4_STRT BIT(4)
#define STM32F4_EOC BIT(1)
/* STM32F4_ADC_CR1 - bit fields */
#define STM32F4_RES_SHIFT 24
#define STM32F4_RES_MASK GENMASK(25, 24)
#define STM32F4_SCAN BIT(8)
#define STM32F4_EOCIE BIT(5)
/* STM32F4_ADC_CR2 - bit fields */
#define STM32F4_SWSTART BIT(30)
#define STM32F4_EXTEN_SHIFT 28
#define STM32F4_EXTEN_MASK GENMASK(29, 28)
#define STM32F4_EXTSEL_SHIFT 24
#define STM32F4_EXTSEL_MASK GENMASK(27, 24)
#define STM32F4_EOCS BIT(10)
#define STM32F4_DDS BIT(9)
#define STM32F4_DMA BIT(8)
#define STM32F4_ADON BIT(0)
/* STM32H7 - Registers for each ADC instance */
#define STM32H7_ADC_ISR 0x00
#define STM32H7_ADC_IER 0x04
#define STM32H7_ADC_CR 0x08
#define STM32H7_ADC_CFGR 0x0C
#define STM32H7_ADC_SMPR1 0x14
#define STM32H7_ADC_SMPR2 0x18
#define STM32H7_ADC_PCSEL 0x1C
#define STM32H7_ADC_SQR1 0x30
#define STM32H7_ADC_SQR2 0x34
#define STM32H7_ADC_SQR3 0x38
#define STM32H7_ADC_SQR4 0x3C
#define STM32H7_ADC_DR 0x40
#define STM32H7_ADC_DIFSEL 0xC0
#define STM32H7_ADC_CALFACT 0xC4
#define STM32H7_ADC_CALFACT2 0xC8
/* STM32H7_ADC_ISR - bit fields */
#define STM32MP1_VREGREADY BIT(12)
#define STM32H7_EOC BIT(2)
#define STM32H7_ADRDY BIT(0)
/* STM32H7_ADC_IER - bit fields */
#define STM32H7_EOCIE STM32H7_EOC
/* STM32H7_ADC_CR - bit fields */
#define STM32H7_ADCAL BIT(31)
#define STM32H7_ADCALDIF BIT(30)
#define STM32H7_DEEPPWD BIT(29)
#define STM32H7_ADVREGEN BIT(28)
#define STM32H7_LINCALRDYW6 BIT(27)
#define STM32H7_LINCALRDYW5 BIT(26)
#define STM32H7_LINCALRDYW4 BIT(25)
#define STM32H7_LINCALRDYW3 BIT(24)
#define STM32H7_LINCALRDYW2 BIT(23)
#define STM32H7_LINCALRDYW1 BIT(22)
#define STM32H7_ADCALLIN BIT(16)
#define STM32H7_BOOST BIT(8)
#define STM32H7_ADSTP BIT(4)
#define STM32H7_ADSTART BIT(2)
#define STM32H7_ADDIS BIT(1)
#define STM32H7_ADEN BIT(0)
/* STM32H7_ADC_CFGR bit fields */
#define STM32H7_EXTEN_SHIFT 10
#define STM32H7_EXTEN_MASK GENMASK(11, 10)
#define STM32H7_EXTSEL_SHIFT 5
#define STM32H7_EXTSEL_MASK GENMASK(9, 5)
#define STM32H7_RES_SHIFT 2
#define STM32H7_RES_MASK GENMASK(4, 2)
#define STM32H7_DMNGT_SHIFT 0
#define STM32H7_DMNGT_MASK GENMASK(1, 0)
enum stm32h7_adc_dmngt {
STM32H7_DMNGT_DR_ONLY, /* Regular data in DR only */
STM32H7_DMNGT_DMA_ONESHOT, /* DMA one shot mode */
STM32H7_DMNGT_DFSDM, /* DFSDM mode */
STM32H7_DMNGT_DMA_CIRC, /* DMA circular mode */
};
/* STM32H7_ADC_CALFACT - bit fields */
#define STM32H7_CALFACT_D_SHIFT 16
#define STM32H7_CALFACT_D_MASK GENMASK(26, 16)
#define STM32H7_CALFACT_S_SHIFT 0
#define STM32H7_CALFACT_S_MASK GENMASK(10, 0)
/* STM32H7_ADC_CALFACT2 - bit fields */
#define STM32H7_LINCALFACT_SHIFT 0
#define STM32H7_LINCALFACT_MASK GENMASK(29, 0)
/* Number of linear calibration shadow registers / LINCALRDYW control bits */ /* Number of linear calibration shadow registers / LINCALRDYW control bits */
#define STM32H7_LINCALFACT_NUM 6 #define STM32H7_LINCALFACT_NUM 6