• Fabrice Gasnier's avatar
    iio: adc: stm32-adc: fix a race when using several adcs with dma and irq · dcb10920
    Fabrice Gasnier authored
    End of conversion may be handled by using IRQ or DMA. There may be a
    race when two conversions complete at the same time on several ADCs.
    EOC can be read as 'set' for several ADCs, with:
    - an ADC configured to use IRQs. EOCIE bit is set. The handler is normally
      called in this case.
    - an ADC configured to use DMA. EOCIE bit isn't set. EOC triggers the DMA
      request instead. It's then automatically cleared by DMA read. But the
      handler gets called due to status bit is temporarily set (IRQ triggered
      by the other ADC).
    So both EOC status bit in CSR and EOCIE control bit must be checked
    before invoking the interrupt handler (e.g. call ISR only for
    IRQ-enabled ADCs).
    Fixes: 2763ea05 ("iio: adc: stm32: add optional dma support")
    Signed-off-by: default avatarFabrice Gasnier <fabrice.gasnier@st.com>
    Cc: <Stable@vger.kernel.org>
    Signed-off-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
stm32-adc-core.c 21.9 KB