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    • Alyssa Rosenzweig's avatar
      pan/midgard: Support indirect UBO offsets · 59d30fd4
      Alyssa Rosenzweig authored
      
      
      ...in case we have arrays in a UBO block that we'd like to access
      indirectly.
      
      Signed-off-by: default avatarAlyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
      Tested-by: Marge Bot <!3352>
      Part-of: <!3352>
      59d30fd4
    • Francisco Jerez's avatar
      intel/fs: Make implied_mrf_writes() an fs_inst method. · c20dc9b8
      Francisco Jerez authored
      
      
      This will be convenient in a later commit enabling SIMD32 fragment
      shaders, and happens to fix the calculation for MATH instructions
      which is currently inaccurate for SIMD-lowered instructions on Gen4-5
      platforms (all of them on Gen4 in SIMD16 mode), since it was based on
      the shader's dispatch width rather than on the actual execution size
      of the instruction.
      
      This causes some shader-db noise on Gen4 due to the more compact
      register allocation interacting with the SEND dependency workarounds,
      but otherwise no major changes.
      
      Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
      c20dc9b8
    • Francisco Jerez's avatar
      intel/fs/cse: Fix non-deterministic behavior due to inaccurate liveness calculation. · 591f146f
      Francisco Jerez authored
      
      
      The liveness calculation done by the local CSE pass in order to prune
      AEB entries whose sources are no longer live is currently inaccurate,
      because the live intervals are calculated once at the beginning of the
      pass, so they don't take into account any of the copy instructions
      inserted by the CSE pass as it makes progress.  However the IP counter
      used in that calculation is based on the start_ip of the basic block,
      which is updated automatically whenever any instructions are inserted
      into the CFG.  This causes the IP counter and liveness intervals to
      get out of sync in programs with multiple basic blocks, causing the
      CSE pass to toss AEB entries prematurely, which can lead to missed
      optimization opportunities rather non-deterministically.
      
      On BDW this leads to the following shader-db changes:
      
       total instructions in shared programs: 14952488 -> 14951763 (-0.00%)
       instructions in affected programs: 45416 -> 44691 (-1.60%)
       helped: 40
       HURT: 4
      
       total spills in shared programs: 20989 -> 20970 (-0.09%)
       spills in affected programs: 103 -> 84 (-18.45%)
       helped: 3
       HURT: 0
      
       total fills in shared programs: 24981 -> 24926 (-0.22%)
       fills in affected programs: 127 -> 72 (-43.31%)
       helped: 3
       HURT: 0
      
      In addition it avoids a number of regressions in combination with some
      of the optimization changes I'm working on for SIMD32, which would
      have made CSE more effective...  Causing it to be less effective
      elsewhere in the program astonishingly.
      
      Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
      591f146f
    • Francisco Jerez's avatar
      intel/fs: Fix nir_intrinsic_load_barycentric_at_sample for SIMD32. · cc0ea482
      Francisco Jerez authored
      
      
      For uniform sample ID, only the first channel of msg_data will be
      initialized.  We need to pass that component only to the SEND message
      for SIMD lowering to unzip the descriptor source correctly.
      
      Fixes several dozens of conformance test failures with SIMD32 fragment
      shaders enabled, including:
      
      dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_sample.dynamic_sample_number.*
      
      Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
      cc0ea482
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