Commits · 3483b4e24c78d186bd67a19f99f891c8e7591a98 · Tomeu Vizoso / mesa

31 Dec, 2020 2 commits

Alyssa Rosenzweig authored Dec 28, 2020



Need to free up the symbol so it doesn't clash with the builder.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8135>

3483b4e2

pan/bi: Ensure fneg of a constant isn't reached · 7af46aa6

Alyssa Rosenzweig authored Dec 22, 2020



Fix the optimization loop like ir3 does.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8135>

7af46aa6

23 Dec, 2020 8 commits

pan/bi: Merge BIR_INDEX_FAU and BIR_INDEX_BLEND · 98fabee2

Alyssa Rosenzweig authored Nov 27, 2020



There's no reason to separate these, and it's more convenient not to.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8215>

98fabee2

pan/bi: Use canonical name for segments · 876f37ed

Alyssa Rosenzweig authored Nov 27, 2020


Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8213>

876f37ed

pan/bi: Use canonical update modes · c7e49426

Alyssa Rosenzweig authored Nov 27, 2020


Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8213>

c7e49426

pan/bi: Use canonical sample names · 3797fc9a

Alyssa Rosenzweig authored Nov 27, 2020


Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8213>

3797fc9a

pan/bi: Use canonical varying names · 2e84a1b4

Alyssa Rosenzweig authored Nov 27, 2020


Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8213>

2e84a1b4

pan/bi: Use canonical names for rounding modes · 030854a3
Alyssa Rosenzweig authored Nov 27, 2020
```
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8213>
```
030854a3

pan/bi: Use canonical names for clamps · 6e481500

Alyssa Rosenzweig authored Nov 27, 2020



Prepare to generate this enum by correctly naming the open-coded
variant.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8213>

6e481500

pan/bi: Label shader-db shaders · 6a46b38d

Alyssa Rosenzweig authored Dec 16, 2020


Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8213>

6a46b38d

21 Dec, 2020 1 commit

pan/bi: Allow toggling disassembly verbosity · 3071f36c

Alyssa Rosenzweig authored Dec 16, 2020



Verbose mode is especially useful for debugging packing, but otherwise
just gets in the way I find.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!8139>

3071f36c

25 Nov, 2020 8 commits

pan/bi: LOD is a 8.8 fixed point · 0f643bbc

Boris Brezillon authored Nov 17, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7653>

0f643bbc

pan/bi: Always emit a LOD/CUBE word for FETCH instructions · 3949e8ba

Boris Brezillon authored Nov 17, 2020



There's no flag/mode to reflect when a LOD is zero on FETCH instructions,
we have to emit the LOD/CUBE word unconditionally.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7653>

3949e8ba

pan/bi: Only update LOD mode on TEX operations · 8040b797

Boris Brezillon authored Nov 17, 2020



If we don't add this check we clobber fetch mode when a 0 LOD is
specified on a txf instruction.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7653>

8040b797

pan/bi: Implement shader-db stats · d299c2eb

Alyssa Rosenzweig authored Nov 13, 2020



v2: Drop register tracking since it was wrong, and meaningful accounting
is tricky for Bifrost (which wants round robin RA for at least some
registers)... we'll cross that bridge when we get there, possibly
preferring a "max liveness" estimate to the raw RA output.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <mesa/mesa!7615>

d299c2eb

pan/bi: Ensure TEXC src0 is not marked SSA · 45de02bd

Alyssa Rosenzweig authored Nov 24, 2020



Prevents attempts to spill tied TEXC src/dest, resulting in a crash,
seen in shaders/tesseract/229.shader_test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <mesa/mesa!7615>

45de02bd

pan/bi: Emit a combine even if we only pass one staging reg to TEXC · bbd3a8ea

Boris Brezillon authored Nov 17, 2020



We need that to account for potential swizzling on the source reg.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <mesa/mesa!7615>

bbd3a8ea

pan/bi: Fix varying writemask handling · 087e3f8d

Alyssa Rosenzweig authored Nov 13, 2020



Allows shaders/supertuxkart/1.shader_test and
shaders/unity/24-Tree.shader_test to compile.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <mesa/mesa!7615>

087e3f8d

pan/bi: Implement sampler1D · eee2a434

Alyssa Rosenzweig authored Nov 13, 2020



Enough to get shaders/humus-celshading/1.shader_test compiling, no idea
if it actually works but it looks reasonable.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <mesa/mesa!7615>

eee2a434

18 Nov, 2020 1 commit
- panfrost/util: Move nir_undef_to_zero into core nir and add 'lower' · b94b827a
  Jesse Natalie authored Jun 02, 2020
```
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7565>
```
  b94b827a
17 Nov, 2020 8 commits

pan/bi: Stop extracting the immediate attribute index from src0 · fee4e991

Boris Brezillon authored Nov 16, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

fee4e991

pan/bi: Fix LD_VAR with non-constant index · fb01328d

Boris Brezillon authored Nov 16, 2020



src0 and src1 were mixed leading to invalid varying indices. In order to
fix that properly, we first extend load_vary to pass the immediate index
through a dedicated field and add a special boolean. This way, we don't
have to make sure src0 always contains the index, and can instead match
the src numbering defined in ISA.xml.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

fb01328d

pan/bi: Stop passing special varying names through src0 · d86973d9

Boris Brezillon authored Nov 16, 2020



It's just clearer to have dedicated fields encoding the fact that the
LD_VAR should be SPECIAL, and another field storing the special var id.

With this change, the source index know matches the ISA.xml definition.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

d86973d9

pan/bi: Pass LD_VAR update mode explicitly · 1176cc12

Boris Brezillon authored Nov 16, 2020



Let the compiler pass the update mode instead of inferring from the
constant value.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

1176cc12

pan/bi: Set roundmode to RTZ for f2u operations · 058bcf44

Boris Brezillon authored Nov 12, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

058bcf44

pan/bi: Let the GPU pick the right format based on the varying descriptor · 00a6a9bd

Boris Brezillon authored Nov 12, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

00a6a9bd

pan/bi: Support txs operations · d0cd8bf2

Boris Brezillon authored Nov 12, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

d0cd8bf2

pan/bi: Don't use TEXS for tex operations with a src that's not lod or coord · 045ae543

Boris Brezillon authored Nov 12, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7636>

045ae543

13 Nov, 2020 4 commits

pan/bi: Add support for tex offsets · 54a965b1

Boris Brezillon authored Nov 09, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7530>

54a965b1

pan/bi: Add support for derivative instructions · 55cb921f

Boris Brezillon authored Nov 12, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7530>

55cb921f

pan/bi: Store the architecture in the compiler context · 9f640c0f

Boris Brezillon authored Nov 12, 2020



Some instructions differ between v6 and v7 and we'll need to know which
architecture we're compiling for if we want to generate the right
instructions.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7530>

9f640c0f

pan/bi: Extract shadowmap comparator · 8be54474

Boris Brezillon authored Nov 09, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7530>

8be54474

09 Nov, 2020 8 commits

pan/bi: Add support for load_instance_id · d47969eb

Boris Brezillon authored Nov 09, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7472>

d47969eb

pan/bi: Add support for load_vertex_id · 5cd1d8c1

Boris Brezillon authored Nov 06, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7472>

5cd1d8c1

pan/bi: Add support for ushr · 4995a4c0

Boris Brezillon authored Nov 06, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7472>

4995a4c0

pan/bi: Add support for ishr · af70987b

Boris Brezillon authored Nov 06, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7472>

af70987b

pan/bi: Get rid of bi_emit_ld_uniform() · cc095072

Boris Brezillon authored Nov 06, 2020



Now that we lower uniforms to UBO we can get rid of bi_emit_ld_uniform().
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7472>

cc095072

pan/bi: Add support for load_ubo · 09da82cb

Boris Brezillon authored Nov 06, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7472>

09da82cb

pan/bi: Fix swizzle handling in bi_copy_src() · 87e2169c

Boris Brezillon authored Nov 05, 2020



The number of src swizzle to initialize depends on the number of source
properties (size and number of components) not the destination ones.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7472>

87e2169c

pan/bi: Support centroid and sample interpolations · 2522f509

Boris Brezillon authored Nov 05, 2020


Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <mesa/mesa!7472>

2522f509