From a782b0b196b2fe1d92b84a69ce19cbaecf121b52 Mon Sep 17 00:00:00 2001
From: Rob Clark <robdclark@chromium.org>
Date: Tue, 27 Apr 2021 09:40:25 -0700
Subject: [PATCH] HACK: iommu/arm-smmu/qcom: Set SCTLR.HUPCF for everything
Currently this is just set from the special qcom,adreno-smmu iommu. But
we are not *yet* using that for a5xx. Meanwhile we still need the HUPCF
bit set so iommu faults in CI do not take out the CP and cause a follow-
on cascade of fail. On qcom systems, it is safe to set HUPCF everywhere
so do that.
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
index 40503376d80cc..e2948b84594e0 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c
@@ -401,6 +401,7 @@ static const struct arm_smmu_impl qcom_smmu_v2_impl = {
.def_domain_type = qcom_smmu_def_domain_type,
.write_s2cr = qcom_smmu_write_s2cr,
.tlb_sync = qcom_smmu_tlb_sync,
+ .write_sctlr = qcom_adreno_smmu_write_sctlr,
};
static const struct arm_smmu_impl qcom_smmu_500_impl = {
--
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