diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index 18d158d77aba699db91f84ddf0f753cb4f199af9..d752db5669dd37788804e983d52b5b24e46fdc26 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -465,6 +465,9 @@
 #define   GEN9_PGCTL_SSB_EU210_ACK		(1 << 12)
 #define   GEN9_PGCTL_SSB_EU311_ACK		(1 << 14)
 
+#define VF_PREEMPTION				_MMIO(0x83a4)
+#define   PREEMPTION_VERTEX_COUNT		REG_GENMASK(15, 0)
+
 #define GEN8_RC6_CTX_INFO			_MMIO(0x8504)
 
 #define GEN12_SQCM				_MMIO(0x8724)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b3067aed7f3ec60cae6cc5bc24cb65e9642f3ce8..0471d475e680fa24bee68167ce7af71bb5a9229e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -683,6 +683,11 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
 	/* Wa_16013271637:dg2 */
 	wa_masked_en(wal, SLICE_COMMON_ECO_CHICKEN1,
 		     MSC_MSAA_REODER_BUF_BYPASS_DISABLE);
+
+	/* Wa_14014947963:dg2 */
+	if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||
+		IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
+		wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000);
 }
 
 static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,