From 0a9c25e119e02ce936bb02ffc4dc432db66dac0b Mon Sep 17 00:00:00 2001
From: Tomeu Vizoso <tomeu@tomeuvizoso.net>
Date: Sun, 9 Jun 2024 09:23:09 +0200
Subject: [PATCH] arm64: dts: rockchip: Add nodes for NPU and its MMU to
rk3588s
See Chapter 36 "RKNN" from the RK3588 TRM (Part 1).
This is a derivative of NVIDIA's NVDLA, but with its own front-end
processor.
Mostly taken from downstream.
Signed-off-by: Tomeu Vizoso <tomeu@tomeuvizoso.net>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 53 +++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index b6e4df180f0b0..fd49872bda10e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1122,6 +1122,59 @@ power-domain@RK3588_PD_SDMMC {
};
};
+ rknn: npu@fdab0000 {
+ compatible = "rockchip,rk3588-rknn", "rockchip,rknn";
+ reg = <0x0 0xfdab0000 0x0 0x9000>,
+ <0x0 0xfdac0000 0x0 0x9000>,
+ <0x0 0xfdad0000 0x0 0x9000>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq";
+ clocks = <&scmi_clk SCMI_CLK_NPU>, <&cru ACLK_NPU0>,
+ <&cru ACLK_NPU1>, <&cru ACLK_NPU2>,
+ <&cru HCLK_NPU0>, <&cru HCLK_NPU1>,
+ <&cru HCLK_NPU2>, <&cru PCLK_NPU_ROOT>;
+ clock-names = "clk_npu",
+ "aclk0", "aclk1", "aclk2",
+ "hclk0", "hclk1", "hclk2",
+ "pclk";
+ assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
+ assigned-clock-rates = <200000000>;
+ resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, <&cru SRST_A_RKNN2>,
+ <&cru SRST_H_RKNN0>, <&cru SRST_H_RKNN1>, <&cru SRST_H_RKNN2>;
+ reset-names = "srst_a0", "srst_a1", "srst_a2",
+ "srst_h0", "srst_h1", "srst_h2";
+ power-domains = <&power RK3588_PD_NPUTOP>,
+ <&power RK3588_PD_NPU1>,
+ <&power RK3588_PD_NPU2>;
+ power-domain-names = "npu0", "npu1", "npu2";
+ iommus = <&rknn_mmu>;
+ status = "disabled";
+ };
+
+ rknn_mmu: iommu@fdab9000 {
+ compatible = "rockchip,rk3588-iommu";
+ reg = <0x0 0xfdab9000 0x0 0x100>,
+ <0x0 0xfdaba000 0x0 0x100>,
+ <0x0 0xfdaca000 0x0 0x100>,
+ <0x0 0xfdada000 0x0 0x100>;
+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "npu0_mmu", "npu1_mmu", "npu2_mmu";
+ clocks = <&cru ACLK_NPU0>, <&cru ACLK_NPU1>, <&cru ACLK_NPU2>,
+ <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, <&cru HCLK_NPU2>;
+ clock-names = "aclk0", "aclk1", "aclk2",
+ "iface0", "iface1", "iface2";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3588_PD_NPUTOP>,
+ <&power RK3588_PD_NPU1>,
+ <&power RK3588_PD_NPU2>;
+ power-domain-names = "npu0", "npu1", "npu2";
+ status = "disabled";
+ };
+
av1d: video-codec@fdc70000 {
compatible = "rockchip,rk3588-av1-vpu";
reg = <0x0 0xfdc70000 0x0 0x800>;
--
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