...
 
Commits (220)
......@@ -98,6 +98,11 @@ ifeq ($(filter 5 6 7 8 9, $(MESA_ANDROID_MAJOR_VERSION)),)
LOCAL_CFLAGS += -DHAVE_TIMESPEC_GET
endif
# Android's libc began supporting shm in Oreo
ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 26 && echo true),true)
LOCAL_CFLAGS += -DHAVE_SYS_SHM_H
endif
ifeq ($(strip $(MESA_ENABLE_ASM)),true)
ifeq ($(TARGET_ARCH),x86)
LOCAL_CFLAGS += \
......
......@@ -15,6 +15,22 @@
<div class="content">
<h1>News</h1>
<h2>June 25, 2019</h2>
<p>
<a href="relnotes/19.1.1.html">Mesa 19.1.1</a> is released.
This is a bug-fix release.
</p>
<h2>June 24, 2019</h2>
<p>
<a href="relnotes/19.0.7.html">Mesa 19.0.7</a> is released.
This is a bug-fix release.
</p>
<p>
NOTE: It is anticipated that 19.0.7 will be the final release in the
19.0 series. Users of 19.0 are encouraged to migrate to the 19.1
series in order to obtain future fixes.
</p>
<h2>June 11, 2019</h2>
<p>
<a href="relnotes/19.1.0.html">Mesa 19.1.0</a> is released.
......
......@@ -60,20 +60,7 @@ if you'd like to nominate a patch in the next stable release.
<th>Notes</th>
</tr>
<tr>
<td rowspan="1">19.0</td>
<td>2019-06-19</td>
<td>19.0.7</td>
<td>Dylan Baker</td>
<td>Last planned 19.0.x release</td>
</tr>
<tr>
<td rowspan="7">19.1</td>
<td>2019-06-25</td>
<td>19.1.1</td>
<td>Juan A. Suarez</td>
<td>
</tr>
<tr>
<td rowspan="6">19.1</td>
<td>2019-07-09</td>
<td>19.1.2</td>
<td>Juan A. Suarez</td>
......
......@@ -21,6 +21,8 @@ The release notes summarize what's new or changed in each Mesa release.
</p>
<ul>
<li><a href="relnotes/19.1.1.html">19.1.1 release notes</a>
<li><a href="relnotes/19.0.7.html">19.0.7 release notes</a>
<li><a href="relnotes/19.1.0.html">19.1.0 release notes</a>
<li><a href="relnotes/19.0.6.html">19.0.6 release notes</a>
<li><a href="relnotes/19.0.5.html">19.0.5 release notes</a>
......
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 19.0.7 Release Notes / June 24, 2019</h1>
<p>
Mesa 19.0.7 is a bug fix release which fixes bugs found since the 19.0.6 release.
</p>
<p>
Mesa 19.0.7 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
81119f0cbbd1fbe7c0574e1e2690e0dae8868124d24c875f5fb76f165db3a54d mesa-19.0.7.tar.gz
d7bf3db2e442fe5eeb96144f8508d94f04aededdf37af477e644638d366b2b28 mesa-19.0.7.tar.xz
</pre>
<h2>New features</h2>
<p>N/A</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110302">Bug 110302</a> - [bisected][regression] piglit egl-create-pbuffer-surface and egl-gl-colorspace regressions</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110921">Bug 110921</a> - virgl on OpenGL 3.3 host regressed to OpenGL 2.1</li>
</ul>
<h2>Changes</h2>
<p>Bas Nieuwenhuizen (5):</p>
<ul>
<li>radv: Prevent out of bound shift on 32-bit builds.</li>
<li>radv: Decompress DCC when the image format is not allowed for buffers.</li>
<li>radv: Fix vulkan build in meson.</li>
<li>anv: Fix vulkan build in meson.</li>
<li>meson: Allow building radeonsi with just the android platform.</li>
</ul>
<p>Charmaine Lee (1):</p>
<ul>
<li>svga: Remove unnecessary check for the pre flush bit for setting vertex buffers</li>
</ul>
<p>Deepak Rawat (1):</p>
<ul>
<li>winsys/svga/drm: Fix 32-bit RPCI send message</li>
</ul>
<p>Dylan Baker (3):</p>
<ul>
<li>docs: Add SHA256 sums for 19.0.6</li>
<li>cherry-ignore: add additional 19.1 only patches</li>
<li>Bump version for 19.0.7 release</li>
</ul>
<p>Emil Velikov (1):</p>
<ul>
<li>mapi: correctly handle the full offset table</li>
</ul>
<p>Gert Wollny (2):</p>
<ul>
<li>virgl: Add a caps feature check version</li>
<li>virgl: Assume sRGB write control for older guest kernels or virglrenderer hosts</li>
</ul>
<p>Haihao Xiang (1):</p>
<ul>
<li>i965: support UYVY for external import only</li>
</ul>
<p>Jason Ekstrand (2):</p>
<ul>
<li>nir/propagate_invariant: Don't add NULL vars to the hash table</li>
<li>anv: Set STATE_BASE_ADDRESS upper bounds on gen7</li>
</ul>
<p>Kenneth Graunke (1):</p>
<ul>
<li>glsl: Fix out of bounds read in shader_cache_read_program_metadata</li>
</ul>
<p>Kevin Strasser (2):</p>
<ul>
<li>gallium/winsys/kms: Fix dumb buffer bpp</li>
<li>st/mesa: Add rgbx handling for fp formats</li>
</ul>
<p>Lionel Landwerlin (2):</p>
<ul>
<li>intel/perf: fix EuThreadsCount value in performance equations</li>
<li>intel/perf: improve dynamic loading config detection</li>
</ul>
<p>Mathias Fröhlich (1):</p>
<ul>
<li>egl: Don't add hardware device if there is no render node v2.</li>
</ul>
<p>Nanley Chery (1):</p>
<ul>
<li>anv/cmd_buffer: Initalize the clear color struct for CNL+</li>
</ul>
<p>Nataraj Deshpande (1):</p>
<ul>
<li>anv: Fix check for isl_fmt in assert</li>
</ul>
<p>Samuel Pitoiset (5):</p>
<ul>
<li>radv: fix alpha-to-coverage when there is unused color attachments</li>
<li>radv: fix setting CB_SHADER_MASK for dual source blending</li>
<li>radv: fix occlusion queries on VegaM</li>
<li>radv: fix VK_EXT_memory_budget if one heap isn't available</li>
<li>radv: fix FMASK expand with SRGB formats</li>
</ul>
</div>
</body>
</html>
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
<html lang="en">
<head>
<meta http-equiv="content-type" content="text/html; charset=utf-8">
<title>Mesa Release Notes</title>
<link rel="stylesheet" type="text/css" href="../mesa.css">
</head>
<body>
<div class="header">
<h1>The Mesa 3D Graphics Library</h1>
</div>
<iframe src="../contents.html"></iframe>
<div class="content">
<h1>Mesa 19.1.1 Release Notes / June 25, 2019</h1>
<p>
Mesa 19.1.1 is a bug fix release which fixes bugs found since the 19.1.0 release.
</p>
<p>
Mesa 19.1.1 implements the OpenGL 4.5 API, but the version reported by
glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
Some drivers don't support all the features required in OpenGL 4.5. OpenGL
4.5 is <strong>only</strong> available if requested at context creation.
Compatibility contexts may report a lower version depending on each driver.
</p>
<h2>SHA256 checksums</h2>
<pre>
72114b16b4a84373b2acda060fe2bb1d45ea2598efab3ef2d44bdeda74f15581 mesa-19.1.1.tar.xz
</pre>
<h2>New features</h2>
<p>None</p>
<h2>Bug fixes</h2>
<ul>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110709">Bug 110709</a> - g_glxglvnddispatchfuncs.c and glxglvnd.c fail to build with clang 8.0</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110901">Bug 110901</a> - mesa-19.1.0/src/util/futex.h:82: use of out of scope variable ?</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110902">Bug 110902</a> - mesa-19.1.0/src/broadcom/compiler/vir_opt_redundant_flags.c:104]: (style) Same expression</li>
<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=110921">Bug 110921</a> - virgl on OpenGL 3.3 host regressed to OpenGL 2.1</li>
</ul>
<h2>Changes</h2>
<p>Alejandro Piñeiro (1):</p>
<ul>
<li>v3d: fix checking twice auf flag</li>
</ul>
<p>Bas Nieuwenhuizen (5):</p>
<ul>
<li>radv: Skip transitions coming from external queue.</li>
<li>radv: Decompress DCC when the image format is not allowed for buffers.</li>
<li>radv: Fix vulkan build in meson.</li>
<li>anv: Fix vulkan build in meson.</li>
<li>meson: Allow building radeonsi with just the android platform.</li>
</ul>
<p>Dave Airlie (1):</p>
<ul>
<li>nouveau: fix frees in unsupported IR error paths.</li>
</ul>
<p>Eduardo Lima Mitev (1):</p>
<ul>
<li>freedreno/a5xx: Fix indirect draw max_indices calculation</li>
</ul>
<p>Eric Engestrom (3):</p>
<ul>
<li>util/futex: fix dangling pointer use</li>
<li>glx: fix glvnd pointer types</li>
<li>util/os_file: resize buffer to what was actually needed</li>
</ul>
<p>Gert Wollny (1):</p>
<ul>
<li>virgl: Assume sRGB write control for older guest kernels or virglrenderer hosts</li>
</ul>
<p>Haihao Xiang (1):</p>
<ul>
<li>i965: support UYVY for external import only</li>
</ul>
<p>Jason Ekstrand (1):</p>
<ul>
<li>anv: Set STATE_BASE_ADDRESS upper bounds on gen7</li>
</ul>
<p>Juan A. Suarez Romero (2):</p>
<ul>
<li>docs: Add SHA256 sums for 19.1.0</li>
<li>Update version to 19.1.1</li>
</ul>
<p>Kenneth Graunke (2):</p>
<ul>
<li>glsl: Fix out of bounds read in shader_cache_read_program_metadata</li>
<li>iris: Fix iris_flush_and_dirty_history to actually dirty history.</li>
</ul>
<p>Kevin Strasser (2):</p>
<ul>
<li>gallium/winsys/kms: Fix dumb buffer bpp</li>
<li>st/mesa: Add rgbx handling for fp formats</li>
</ul>
<p>Lionel Landwerlin (2):</p>
<ul>
<li>anv: do not parse genxml data without INTEL_DEBUG=bat</li>
<li>intel/dump: fix segfault when the app hasn't accessed the device</li>
</ul>
<p>Mathias Fröhlich (1):</p>
<ul>
<li>egl: Don't add hardware device if there is no render node v2.</li>
</ul>
<p>Richard Thier (1):</p>
<ul>
<li>r300g: restore performance after RADEON_FLAG_NO_INTERPROCESS_SHARING was added</li>
</ul>
<p>Rob Clark (1):</p>
<ul>
<li>freedreno/a6xx: un-swap X24S8_UINT</li>
</ul>
<p>Samuel Pitoiset (4):</p>
<ul>
<li>radv: fix occlusion queries on VegaM</li>
<li>radv: fix VK_EXT_memory_budget if one heap isn't available</li>
<li>radv: fix FMASK expand with SRGB formats</li>
<li>radv: disable viewport clamping even if FS doesn't write Z</li>
</ul>
</div>
</body>
</html>
This diff is collapsed.
This diff is collapsed.
#ifndef __gl_h_
#define __gl_h_ 1
#ifndef __gles1_gl_h_
#define __gles1_gl_h_ 1
#ifdef __cplusplus
extern "C" {
#endif
/*
** Copyright (c) 2013-2017 The Khronos Group Inc.
** Copyright (c) 2013-2018 The Khronos Group Inc.
**
** Permission is hereby granted, free of charge, to any person obtaining a
** copy of this software and/or associated documentation files (the
......@@ -36,7 +36,7 @@ extern "C" {
#include <GLES/glplatform.h>
/* Generated on date 20170606 */
/* Generated on date 20190611 */
/* Generated C header for:
* API: gles1
......@@ -50,20 +50,11 @@ extern "C" {
#ifndef GL_VERSION_ES_CM_1_0
#define GL_VERSION_ES_CM_1_0 1
/*
* XXX: Temporary fix; needs to be reverted as part of the next
* header update.
* For more details:
* https://github.com/KhronosGroup/OpenGL-Registry/pull/76
* https://lists.freedesktop.org/archives/mesa-dev/2017-June/161647.html
*/
#include <KHR/khrplatform.h>
typedef khronos_int8_t GLbyte;
typedef khronos_float_t GLclampf;
typedef short GLshort;
typedef unsigned short GLushort;
typedef khronos_int16_t GLshort;
typedef khronos_uint16_t GLushort;
typedef void GLvoid;
typedef unsigned int GLenum;
typedef khronos_float_t GLfloat;
......
#ifndef __glext_h_
#define __glext_h_ 1
#ifndef __gles1_glext_h_
#define __gles1_glext_h_ 1
#ifdef __cplusplus
extern "C" {
#endif
/*
** Copyright (c) 2013-2017 The Khronos Group Inc.
** Copyright (c) 2013-2018 The Khronos Group Inc.
**
** Permission is hereby granted, free of charge, to any person obtaining a
** copy of this software and/or associated documentation files (the
......@@ -38,7 +38,7 @@ extern "C" {
#define GL_APIENTRYP GL_APIENTRY*
#endif
/* Generated on date 20170606 */
/* Generated on date 20190611 */
/* Generated C header for:
* API: gles1
......@@ -50,6 +50,10 @@ extern "C" {
* Extensions removed: ^(GL_OES_read_format|GL_OES_compressed_paletted_texture|GL_OES_point_size_array|GL_OES_point_sprite)$
*/
#ifndef GL_KHR_debug
#define GL_KHR_debug 1
#endif /* GL_KHR_debug */
#ifndef GL_OES_EGL_image
#define GL_OES_EGL_image 1
typedef void *GLeglImageOES;
......@@ -444,6 +448,11 @@ GL_API void GL_APIENTRY glOrthofOES (GLfloat l, GLfloat r, GLfloat b, GLfloat t,
#define GL_DECR_WRAP_OES 0x8508
#endif /* GL_OES_stencil_wrap */
#ifndef GL_OES_surfaceless_context
#define GL_OES_surfaceless_context 1
#define GL_FRAMEBUFFER_UNDEFINED_OES 0x8219
#endif /* GL_OES_surfaceless_context */
#ifndef GL_OES_texture_cube_map
#define GL_OES_texture_cube_map 1
#define GL_NORMAL_MAP_OES 0x8511
......@@ -484,6 +493,10 @@ GL_API void GL_APIENTRY glGetTexGenivOES (GLenum coord, GLenum pname, GLint *par
#define GL_MIRRORED_REPEAT_OES 0x8370
#endif /* GL_OES_texture_mirrored_repeat */
#ifndef GL_OES_texture_npot
#define GL_OES_texture_npot 1
#endif /* GL_OES_texture_npot */
#ifndef GL_OES_vertex_array_object
#define GL_OES_vertex_array_object 1
#define GL_VERTEX_ARRAY_BINDING_OES 0x85B5
......@@ -601,6 +614,19 @@ GL_API void GL_APIENTRY glGetSyncivAPPLE (GLsync sync, GLenum pname, GLsizei buf
#define GL_MAX_EXT 0x8008
#endif /* GL_EXT_blend_minmax */
#ifndef GL_EXT_debug_marker
#define GL_EXT_debug_marker 1
typedef char GLchar;
typedef void (GL_APIENTRYP PFNGLINSERTEVENTMARKEREXTPROC) (GLsizei length, const GLchar *marker);
typedef void (GL_APIENTRYP PFNGLPUSHGROUPMARKEREXTPROC) (GLsizei length, const GLchar *marker);
typedef void (GL_APIENTRYP PFNGLPOPGROUPMARKEREXTPROC) (void);
#ifdef GL_GLEXT_PROTOTYPES
GL_API void GL_APIENTRY glInsertEventMarkerEXT (GLsizei length, const GLchar *marker);
GL_API void GL_APIENTRY glPushGroupMarkerEXT (GLsizei length, const GLchar *marker);
GL_API void GL_APIENTRY glPopGroupMarkerEXT (void);
#endif
#endif /* GL_EXT_debug_marker */
#ifndef GL_EXT_discard_framebuffer
#define GL_EXT_discard_framebuffer 1
#define GL_COLOR_EXT 0x1800
......@@ -829,7 +855,6 @@ GL_API void GL_APIENTRY glSetFenceNV (GLuint fence, GLenum condition);
#ifndef GL_QCOM_driver_control
#define GL_QCOM_driver_control 1
typedef char GLchar;
typedef void (GL_APIENTRYP PFNGLGETDRIVERCONTROLSQCOMPROC) (GLint *num, GLsizei size, GLuint *driverControls);
typedef void (GL_APIENTRYP PFNGLGETDRIVERCONTROLSTRINGQCOMPROC) (GLuint driverControl, GLsizei bufSize, GLsizei *length, GLchar *driverControlString);
typedef void (GL_APIENTRYP PFNGLENABLEDRIVERCONTROLQCOMPROC) (GLuint driverControl);
......
......@@ -44,7 +44,7 @@ extern "C" {
#define GL_GLES_PROTOTYPES 1
#endif
/* Generated on date 20180725 */
/* Generated on date 20190611 */
/* Generated C header for:
* API: gles2
......@@ -62,8 +62,8 @@ extern "C" {
typedef khronos_int8_t GLbyte;
typedef khronos_float_t GLclampf;
typedef khronos_int32_t GLfixed;
typedef short GLshort;
typedef unsigned short GLushort;
typedef khronos_int16_t GLshort;
typedef khronos_uint16_t GLushort;
typedef void GLvoid;
typedef struct __GLsync *GLsync;
typedef khronos_int64_t GLint64;
......
This diff is collapsed.
......@@ -44,7 +44,7 @@ extern "C" {
#define GL_GLES_PROTOTYPES 1
#endif
/* Generated on date 20180725 */
/* Generated on date 20190611 */
/* Generated C header for:
* API: gles2
......@@ -62,8 +62,8 @@ extern "C" {
typedef khronos_int8_t GLbyte;
typedef khronos_float_t GLclampf;
typedef khronos_int32_t GLfixed;
typedef short GLshort;
typedef unsigned short GLushort;
typedef khronos_int16_t GLshort;
typedef khronos_uint16_t GLushort;
typedef void GLvoid;
typedef struct __GLsync *GLsync;
typedef khronos_int64_t GLint64;
......@@ -670,7 +670,7 @@ GL_APICALL void GL_APIENTRY glViewport (GLint x, GLint y, GLsizei width, GLsizei
#ifndef GL_ES_VERSION_3_0
#define GL_ES_VERSION_3_0 1
typedef unsigned short GLhalf;
typedef khronos_uint16_t GLhalf;
#define GL_READ_BUFFER 0x0C02
#define GL_UNPACK_ROW_LENGTH 0x0CF2
#define GL_UNPACK_SKIP_ROWS 0x0CF3
......
#ifndef __gl31_h_
#define __gl31_h_ 1
#ifndef __gles2_gl31_h_
#define __gles2_gl31_h_ 1
#ifdef __cplusplus
extern "C" {
#endif
/*
** Copyright (c) 2013-2016 The Khronos Group Inc.
** Copyright (c) 2013-2018 The Khronos Group Inc.
**
** Permission is hereby granted, free of charge, to any person obtaining a
** copy of this software and/or associated documentation files (the
......@@ -31,9 +31,7 @@ extern "C" {
** This header is generated from the Khronos OpenGL / OpenGL ES XML
** API Registry. The current version of the Registry, generator scripts
** used to make the header, and the header can be found at
** http://www.opengl.org/registry/
**
** Khronos $Revision$ on $Date$
** https://github.com/KhronosGroup/OpenGL-Registry
*/
#include <GLES3/gl3platform.h>
......@@ -46,7 +44,7 @@ extern "C" {
#define GL_GLES_PROTOTYPES 1
#endif
/* Generated on date 20161024 */
/* Generated on date 20190611 */
/* Generated C header for:
* API: gles2
......@@ -64,8 +62,8 @@ extern "C" {
typedef khronos_int8_t GLbyte;
typedef khronos_float_t GLclampf;
typedef khronos_int32_t GLfixed;
typedef short GLshort;
typedef unsigned short GLushort;
typedef khronos_int16_t GLshort;
typedef khronos_uint16_t GLushort;
typedef void GLvoid;
typedef struct __GLsync *GLsync;
typedef khronos_int64_t GLint64;
......@@ -672,7 +670,7 @@ GL_APICALL void GL_APIENTRY glViewport (GLint x, GLint y, GLsizei width, GLsizei
#ifndef GL_ES_VERSION_3_0
#define GL_ES_VERSION_3_0 1
typedef unsigned short GLhalf;
typedef khronos_uint16_t GLhalf;
#define GL_READ_BUFFER 0x0C02
#define GL_UNPACK_ROW_LENGTH 0x0CF2
#define GL_UNPACK_SKIP_ROWS 0x0CF3
......
#ifndef __gl32_h_
#define __gl32_h_ 1
#ifndef __gles2_gl32_h_
#define __gles2_gl32_h_ 1
#ifdef __cplusplus
extern "C" {
#endif
/*
** Copyright (c) 2013-2016 The Khronos Group Inc.
** Copyright (c) 2013-2018 The Khronos Group Inc.
**
** Permission is hereby granted, free of charge, to any person obtaining a
** copy of this software and/or associated documentation files (the
......@@ -31,9 +31,7 @@ extern "C" {
** This header is generated from the Khronos OpenGL / OpenGL ES XML
** API Registry. The current version of the Registry, generator scripts
** used to make the header, and the header can be found at
** http://www.opengl.org/registry/
**
** Khronos $Revision$ on $Date$
** https://github.com/KhronosGroup/OpenGL-Registry
*/
#include <GLES3/gl3platform.h>
......@@ -46,7 +44,7 @@ extern "C" {
#define GL_GLES_PROTOTYPES 1
#endif
/* Generated on date 20161024 */
/* Generated on date 20190611 */
/* Generated C header for:
* API: gles2
......@@ -64,8 +62,8 @@ extern "C" {
typedef khronos_int8_t GLbyte;
typedef khronos_float_t GLclampf;
typedef khronos_int32_t GLfixed;
typedef short GLshort;
typedef unsigned short GLushort;
typedef khronos_int16_t GLshort;
typedef khronos_uint16_t GLushort;
typedef void GLvoid;
typedef struct __GLsync *GLsync;
typedef khronos_int64_t GLint64;
......@@ -672,7 +670,7 @@ GL_APICALL void GL_APIENTRY glViewport (GLint x, GLint y, GLsizei width, GLsizei
#ifndef GL_ES_VERSION_3_0
#define GL_ES_VERSION_3_0 1
typedef unsigned short GLhalf;
typedef khronos_uint16_t GLhalf;
#define GL_READ_BUFFER 0x0C02
#define GL_UNPACK_ROW_LENGTH 0x0CF2
#define GL_UNPACK_SKIP_ROWS 0x0CF3
......
......@@ -224,6 +224,8 @@ CHIPSET(0x5A54, cnl_5x8, "Intel(R) HD Graphics (Cannonlake 5x8 GT2)")
CHIPSET(0x8A50, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
CHIPSET(0x8A51, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
CHIPSET(0x8A52, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
CHIPSET(0x8A53, icl_8x8, "Intel(R) HD Graphics (Ice Lake 8x8 GT2)")
CHIPSET(0x8A54, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
CHIPSET(0x8A56, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
CHIPSET(0x8A57, icl_6x8, "Intel(R) HD Graphics (Ice Lake 6x8 GT1.5)")
CHIPSET(0x8A58, icl_4x8, "Intel(R) HD Graphics (Ice Lake 4x8 GT1)")
......
......@@ -278,6 +278,10 @@ with_platform_surfaceless = _platforms.contains('surfaceless')
with_platforms = false
if _platforms.length() != 0 and _platforms != ['']
# sanity check that list contains no empty strings
if _platforms.contains('')
error('Invalid argument list given to -Dplatforms, please fix.')
endif
with_platforms = true
egl_native_platform = _platforms[0]
endif
......@@ -1036,7 +1040,7 @@ elif cc.has_header_symbol('sys/mkdev.h', 'major')
pre_args += '-DMAJOR_IN_MKDEV'
endif
foreach h : ['xlocale.h', 'sys/sysctl.h', 'linux/futex.h', 'endian.h', 'dlfcn.h', 'execinfo.h']
foreach h : ['xlocale.h', 'sys/sysctl.h', 'linux/futex.h', 'endian.h', 'dlfcn.h', 'execinfo.h', 'sys/shm.h']
if cc.compiles('#include <@0@>'.format(h), name : '@0@'.format(h))
pre_args += '-DHAVE_@0@'.format(h.to_upper().underscorify())
endif
......
......@@ -371,6 +371,9 @@ def generate(env):
if check_functions(env, ['timespec_get']):
cppdefines += ['HAVE_TIMESPEC_GET']
if check_header(env, 'sys/shm.h'):
cppdefines += ['HAVE_SYS_SHM_H']
if platform == 'windows':
cppdefines += [
'WIN32',
......
......@@ -62,7 +62,8 @@ LOCAL_C_INCLUDES := \
$(intermediates)/common
LOCAL_EXPORT_C_INCLUDE_DIRS := \
$(LOCAL_PATH)/common
$(LOCAL_PATH)/common \
$(intermediates)/common
LOCAL_SHARED_LIBRARIES := \
libdrm_amdgpu
......
......@@ -335,6 +335,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
return false;
}
info->family_id = amdinfo->family_id;
info->chip_external_rev = amdinfo->chip_external_rev;
info->marketing_name = amdgpu_get_marketing_name(dev);
info->is_pro_graphics = info->marketing_name &&
(!strcmp(info->marketing_name, "Pro") ||
......
......@@ -53,6 +53,8 @@ struct radeon_info {
uint32_t pci_id;
enum radeon_family family;
enum chip_class chip_class;
uint32_t family_id;
uint32_t chip_external_rev;
uint32_t num_compute_rings;
uint32_t num_sdma_rings;
uint32_t clock_crystal_freq;
......
......@@ -2798,11 +2798,22 @@ LLVMValueRef ac_build_bfe(struct ac_llvm_context *ctx, LLVMValueRef input,
width,
};
return ac_build_intrinsic(ctx,
is_signed ? "llvm.amdgcn.sbfe.i32" :
"llvm.amdgcn.ubfe.i32",
ctx->i32, args, 3,
AC_FUNC_ATTR_READNONE);
LLVMValueRef result = ac_build_intrinsic(ctx,
is_signed ? "llvm.amdgcn.sbfe.i32" :
"llvm.amdgcn.ubfe.i32",
ctx->i32, args, 3,
AC_FUNC_ATTR_READNONE);
if (HAVE_LLVM < 0x0800) {
/* FIXME: LLVM 7+ returns incorrect result when count is 0.
* https://bugs.freedesktop.org/show_bug.cgi?id=107276
*/
LLVMValueRef zero = ctx->i32_0;
LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, width, zero, "");
result = LLVMBuildSelect(ctx->builder, icond, zero, result, "");
}
return result;
}
LLVMValueRef ac_build_imad(struct ac_llvm_context *ctx, LLVMValueRef s0,
......@@ -4434,3 +4445,11 @@ ac_build_load_helper_invocation(struct ac_llvm_context *ctx)
result = LLVMBuildNot(ctx->builder, result, "");
return LLVMBuildSExt(ctx->builder, result, ctx->i32, "");
}
LLVMValueRef ac_build_call(struct ac_llvm_context *ctx, LLVMValueRef func,
LLVMValueRef *args, unsigned num_args)
{
LLVMValueRef ret = LLVMBuildCall(ctx->builder, func, args, num_args, "");
LLVMSetInstructionCallConv(ret, LLVMGetFunctionCallConv(func));
return ret;
}
......@@ -720,6 +720,9 @@ ac_build_ddxy_interp(struct ac_llvm_context *ctx, LLVMValueRef interp_ij);
LLVMValueRef
ac_build_load_helper_invocation(struct ac_llvm_context *ctx);
LLVMValueRef ac_build_call(struct ac_llvm_context *ctx, LLVMValueRef func,
LLVMValueRef *args, unsigned num_args);
LLVMValueRef ac_build_atomic_rmw(struct ac_llvm_context *ctx, LLVMAtomicRMWBinOp op,
LLVMValueRef ptr, LLVMValueRef val,
const char *sync_scope);
......
......@@ -429,60 +429,30 @@ static LLVMValueRef emit_imul_high(struct ac_llvm_context *ctx,
return result;
}
static LLVMValueRef emit_bitfield_extract(struct ac_llvm_context *ctx,
bool is_signed,
const LLVMValueRef srcs[3])
static LLVMValueRef emit_bfm(struct ac_llvm_context *ctx,
LLVMValueRef bits, LLVMValueRef offset)
{
LLVMValueRef result;
if (HAVE_LLVM >= 0x0800) {
LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
result = LLVMBuildSelect(ctx->builder, icond, srcs[0], result, "");
} else {
/* FIXME: LLVM 7+ returns incorrect result when count is 0.
* https://bugs.freedesktop.org/show_bug.cgi?id=107276
*/
LLVMValueRef zero = ctx->i32_0;
LLVMValueRef icond1 = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], LLVMConstInt(ctx->i32, 32, false), "");
LLVMValueRef icond2 = LLVMBuildICmp(ctx->builder, LLVMIntEQ, srcs[2], zero, "");
result = ac_build_bfe(ctx, srcs[0], srcs[1], srcs[2], is_signed);
result = LLVMBuildSelect(ctx->builder, icond1, srcs[0], result, "");
result = LLVMBuildSelect(ctx->builder, icond2, zero, result, "");
}
return result;
/* mask = ((1 << bits) - 1) << offset */
return LLVMBuildShl(ctx->builder,
LLVMBuildSub(ctx->builder,
LLVMBuildShl(ctx->builder,
ctx->i32_1,
bits, ""),
ctx->i32_1, ""),
offset, "");
}
static LLVMValueRef emit_bitfield_insert(struct ac_llvm_context *ctx,
LLVMValueRef src0, LLVMValueRef src1,
LLVMValueRef src2, LLVMValueRef src3)
static LLVMValueRef emit_bitfield_select(struct ac_llvm_context *ctx,
LLVMValueRef mask, LLVMValueRef insert,
LLVMValueRef base)
{
LLVMValueRef bfi_args[3], result;
bfi_args[0] = LLVMBuildShl(ctx->builder,
LLVMBuildSub(ctx->builder,
LLVMBuildShl(ctx->builder,
ctx->i32_1,
src3, ""),
ctx->i32_1, ""),
src2, "");
bfi_args[1] = LLVMBuildShl(ctx->builder, src1, src2, "");
bfi_args[2] = src0;
LLVMValueRef icond = LLVMBuildICmp(ctx->builder, LLVMIntEQ, src3, LLVMConstInt(ctx->i32, 32, false), "");
/* Calculate:
* (arg0 & arg1) | (~arg0 & arg2) = arg2 ^ (arg0 & (arg1 ^ arg2)
* (mask & insert) | (~mask & base) = base ^ (mask & (insert ^ base))
* Use the right-hand side, which the LLVM backend can convert to V_BFI.
*/
result = LLVMBuildXor(ctx->builder, bfi_args[2],
LLVMBuildAnd(ctx->builder, bfi_args[0],
LLVMBuildXor(ctx->builder, bfi_args[1], bfi_args[2], ""), ""), "");
result = LLVMBuildSelect(ctx->builder, icond, src1, result, "");
return result;
return LLVMBuildXor(ctx->builder, base,
LLVMBuildAnd(ctx->builder, mask,
LLVMBuildXor(ctx->builder, insert, base, ""), ""), "");
}
static LLVMValueRef emit_pack_half_2x16(struct ac_llvm_context *ctx,
......@@ -835,14 +805,17 @@ static void visit_alu(struct ac_nir_context *ctx, const nir_alu_instr *instr)
else
result = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ldexp.f64", ctx->ac.f64, src, 2, AC_FUNC_ATTR_READNONE);
break;
case nir_op_ibitfield_extract:
result = emit_bitfield_extract(&ctx->ac, true, src);
case nir_op_bfm:
result = emit_bfm(&ctx->ac, src[0], src[1]);
break;
case nir_op_bitfield_select:
result = emit_bitfield_select(&ctx->ac, src[0], src[1], src[2]);
break;
case nir_op_ubitfield_extract:
result = emit_bitfield_extract(&ctx->ac, false, src);
case nir_op_ubfe:
result = ac_build_bfe(&ctx->ac, src[0], src[1], src[2], false);
break;
case nir_op_bitfield_insert:
result = emit_bitfield_insert(&ctx->ac, src[0], src[1], src[2], src[3]);
case nir_op_ibfe:
result = ac_build_bfe(&ctx->ac, src[0], src[1], src[2], true);
break;
case nir_op_bitfield_reverse:
result = ac_build_bitfield_reverse(&ctx->ac, src[0]);
......
......@@ -39,7 +39,11 @@
#define MY_EM_AMDGPU 224
#ifndef STT_AMDGPU_LDS
#define STT_AMDGPU_LDS 13
#define STT_AMDGPU_LDS 13 // this is deprecated -- remove
#endif
#ifndef SHN_AMDGPU_LDS
#define SHN_AMDGPU_LDS 0xff00
#endif
#ifndef R_AMDGPU_NONE
......@@ -176,13 +180,20 @@ static bool read_private_lds_symbols(struct ac_rtld_binary *binary,
Elf_Scn *section,
uint32_t *lds_end_align)
{
#define report_elf_if(cond) \
#define report_if(cond) \
do { \
if ((cond)) { \
report_errorf(#cond); \
return false; \
} \
} while (false)
#define report_elf_if(cond) \
do { \
if ((cond)) { \
report_elf_errorf(#cond); \
return false; \
} \
} while (false)
struct ac_rtld_part *part = &binary->parts[part_idx];
Elf64_Shdr *shdr = elf64_getshdr(section);
......@@ -194,15 +205,21 @@ static bool read_private_lds_symbols(struct ac_rtld_binary *binary,
size_t num_symbols = symbols_data->d_size / sizeof(Elf64_Sym);
for (size_t j = 0; j < num_symbols; ++j, ++symbol) {
if (ELF64_ST_TYPE(symbol->st_info) != STT_AMDGPU_LDS)
struct ac_rtld_symbol s = {};
if (ELF64_ST_TYPE(symbol->st_info) == STT_AMDGPU_LDS) {
/* old-style LDS symbols from initial prototype -- remove eventually */
s.align = MIN2(1u << (symbol->st_other >> 3), 1u << 16);
} else if (symbol->st_shndx == SHN_AMDGPU_LDS) {
s.align = MIN2(symbol->st_value, 1u << 16);
report_if(!util_is_power_of_two_nonzero(s.align));
} else
continue;
report_elf_if(symbol->st_size > 1u << 29);
report_if(symbol->st_size > 1u << 29);
struct ac_rtld_symbol s = {};
s.name = elf_strptr(part->elf, strtabidx, symbol->st_name);
s.size = symbol->st_size;
s.align = MIN2(1u << (symbol->st_other >> 3), 1u << 16);
s.part_idx = part_idx;
if (!strcmp(s.name, "__lds_end")) {
......@@ -224,6 +241,7 @@ static bool read_private_lds_symbols(struct ac_rtld_binary *binary,
return true;
#undef report_if
#undef report_elf_if
}
......@@ -522,7 +540,9 @@ static bool resolve_symbol(const struct ac_rtld_upload_info *u,
unsigned part_idx, const Elf64_Sym *sym,
const char *name, uint64_t *value)
{
if (sym->st_shndx == SHN_UNDEF) {
/* TODO: properly disentangle the undef and the LDS cases once
* STT_AMDGPU_LDS is retired. */
if (sym->st_shndx == SHN_UNDEF || sym->st_shndx == SHN_AMDGPU_LDS) {
const struct ac_rtld_symbol *lds_sym =
find_symbol(&u->binary->lds_symbols, name, part_idx);
......
......@@ -49,113 +49,6 @@
#define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
#endif
static unsigned get_first(unsigned x, unsigned y)
{
return x;
}
static void addrlib_family_rev_id(enum radeon_family family,
unsigned *addrlib_family,
unsigned *addrlib_revid)
{
switch (family) {
case CHIP_TAHITI:
*addrlib_family = FAMILY_SI;
*addrlib_revid = get_first(AMDGPU_TAHITI_RANGE);
break;
case CHIP_PITCAIRN:
*addrlib_family = FAMILY_SI;
*addrlib_revid = get_first(AMDGPU_PITCAIRN_RANGE);
break;
case CHIP_VERDE:
*addrlib_family = FAMILY_SI;
*addrlib_revid = get_first(AMDGPU_CAPEVERDE_RANGE);
break;
case CHIP_OLAND:
*addrlib_family = FAMILY_SI;
*addrlib_revid = get_first(AMDGPU_OLAND_RANGE);
break;
case CHIP_HAINAN:
*addrlib_family = FAMILY_SI;
*addrlib_revid = get_first(AMDGPU_HAINAN_RANGE);
break;
case CHIP_BONAIRE:
*addrlib_family = FAMILY_CI;
*addrlib_revid = get_first(AMDGPU_BONAIRE_RANGE);
break;
case CHIP_KAVERI:
*addrlib_family = FAMILY_KV;
*addrlib_revid = get_first(AMDGPU_SPECTRE_RANGE);
break;
case CHIP_KABINI:
*addrlib_family = FAMILY_KV;
*addrlib_revid = get_first(AMDGPU_KALINDI_RANGE);
break;
case CHIP_HAWAII:
*addrlib_family = FAMILY_CI;
*addrlib_revid = get_first(AMDGPU_HAWAII_RANGE);
break;
case CHIP_TONGA:
*addrlib_family = FAMILY_VI;
*addrlib_revid = get_first(AMDGPU_TONGA_RANGE);
break;
case CHIP_ICELAND:
*addrlib_family = FAMILY_VI;
*addrlib_revid = get_first(AMDGPU_ICELAND_RANGE);
break;
case CHIP_CARRIZO:
*addrlib_family = FAMILY_CZ;
*addrlib_revid = get_first(AMDGPU_CARRIZO_RANGE);
break;
case CHIP_STONEY:
*addrlib_family = FAMILY_CZ;
*addrlib_revid = get_first(AMDGPU_STONEY_RANGE);
break;
case CHIP_FIJI:
*addrlib_family = FAMILY_VI;
*addrlib_revid = get_first(AMDGPU_FIJI_RANGE);
break;
case CHIP_POLARIS10:
*addrlib_family = FAMILY_VI;
*addrlib_revid = get_first(AMDGPU_POLARIS10_RANGE);
break;
case CHIP_POLARIS11:
*addrlib_family = FAMILY_VI;
*addrlib_revid = get_first(AMDGPU_POLARIS11_RANGE);
break;
case CHIP_POLARIS12:
*addrlib_family = FAMILY_VI;
*addrlib_revid = get_first(AMDGPU_POLARIS12_RANGE);
break;
case CHIP_VEGAM:
*addrlib_family = FAMILY_VI;
*addrlib_revid = get_first(AMDGPU_VEGAM_RANGE);
break;
case CHIP_VEGA10:
*addrlib_family = FAMILY_AI;
*addrlib_revid = get_first(AMDGPU_VEGA10_RANGE);
break;
case CHIP_VEGA12:
*addrlib_family = FAMILY_AI;
*addrlib_revid = get_first(AMDGPU_VEGA12_RANGE);
break;
case CHIP_VEGA20:
*addrlib_family = FAMILY_AI;
*addrlib_revid = get_first(AMDGPU_VEGA20_RANGE);
break;
case CHIP_RAVEN:
*addrlib_family = FAMILY_RV;
*addrlib_revid = get_first(AMDGPU_RAVEN_RANGE);
break;
case CHIP_RAVEN2:
*addrlib_family = FAMILY_RV;
*addrlib_revid = get_first(AMDGPU_RAVEN2_RANGE);
break;
default:
fprintf(stderr, "amdgpu: Unknown family.\n");
}
}
static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
{
return malloc(pInput->sizeInBytes);
......@@ -184,7 +77,9 @@ ADDR_HANDLE amdgpu_addr_create(const struct radeon_info *info,
regValue.gbAddrConfig = amdinfo->gb_addr_cfg;
createFlags.value = 0;
addrlib_family_rev_id(info->family, &addrCreateInput.chipFamily, &addrCreateInput.chipRevision);
addrCreateInput.chipFamily = info->family_id;
addrCreateInput.chipRevision = info->chip_external_rev;
if (addrCreateInput.chipFamily == FAMILY_UNKNOWN)
return NULL;
......@@ -609,7 +504,8 @@ static void ac_compute_cmask(const struct radeon_info *info,
num_layers = config->info.array_size;
surf->cmask_alignment = MAX2(256, base_align);
surf->cmask_size = align(slice_bytes, base_align) * num_layers;
surf->cmask_slice_size = align(slice_bytes, base_align);
surf->cmask_size = surf->cmask_slice_size * num_layers;
}
/**
......@@ -953,6 +849,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
surf->u.legacy.fmask.tiling_index = fout.tileIndex;
surf->u.legacy.fmask.bankh = fout.pTileInfo->bankHeight;
surf->u.legacy.fmask.pitch_in_pixels = fout.pitch;
surf->u.legacy.fmask.slice_size = fout.sliceSize;
/* Compute tile swizzle for FMASK. */
if (config->info.fmask_surf_index &&
......
......@@ -86,6 +86,7 @@ struct legacy_surf_fmask {
uint8_t tiling_index; /* max 31 */
uint8_t bankh; /* max 8 */
uint16_t pitch_in_pixels;
uint64_t slice_size;
};
struct legacy_surf_layout {
......@@ -218,6 +219,7 @@ struct radeon_surf {
uint32_t htile_alignment;
uint32_t cmask_size;
uint32_t cmask_slice_size;
uint32_t cmask_alignment;
union {
......
......@@ -68,7 +68,7 @@ $(call mesa-build-with-llvm)
LOCAL_C_INCLUDES := \
$(RADV_COMMON_INCLUDES) \
$(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_amd_common,,) \
$(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_amd_common,,)/common \
$(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_nir,,)/nir \
$(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_radv_common,,) \
$(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_vulkan_util,,)/util \
......
......@@ -1876,6 +1876,8 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
S_028208_BR_Y(framebuffer->height));
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
bool disable_constant_encode =
cmd_buffer->device->physical_device->has_dcc_constant_encode;
uint8_t watermark = 4; /* Default value for GFX8. */
/* For optimal DCC performance. */
......@@ -1889,7 +1891,8 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,
S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
S_028424_OVERWRITE_COMBINER_WATERMARK(watermark));
S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
S_028424_DISABLE_CONSTANT_ENCODE_REG(disable_constant_encode));
}
if (cmd_buffer->device->dfsm_allowed) {
......@@ -2573,7 +2576,7 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
case VK_ACCESS_SHADER_WRITE_BIT:
case VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT:
case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
flush_bits |= RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
flush_bits |= RADV_CMD_FLAG_WB_L2;
break;
case VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT:
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB;
......@@ -2588,7 +2591,7 @@ radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer,
case VK_ACCESS_TRANSFER_WRITE_BIT:
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_DB |
RADV_CMD_FLAG_INV_GLOBAL_L2;
RADV_CMD_FLAG_INV_L2;
if (flush_CB_meta)
flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
......@@ -2645,19 +2648,19 @@ radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer,
case VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT:
break;
case VK_ACCESS_UNIFORM_READ_BIT:
flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 | RADV_CMD_FLAG_INV_SMEM_L1;
flush_bits |= RADV_CMD_FLAG_INV_VCACHE | RADV_CMD_FLAG_INV_SCACHE;
break;
case VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT:
case VK_ACCESS_TRANSFER_READ_BIT:
case VK_ACCESS_INPUT_ATTACHMENT_READ_BIT:
flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1 |
RADV_CMD_FLAG_INV_GLOBAL_L2;
flush_bits |= RADV_CMD_FLAG_INV_VCACHE |
RADV_CMD_FLAG_INV_L2;
break;
case VK_ACCESS_SHADER_READ_BIT:
flush_bits |= RADV_CMD_FLAG_INV_VMEM_L1;
flush_bits |= RADV_CMD_FLAG_INV_VCACHE;
if (!image_is_coherent)
flush_bits |= RADV_CMD_FLAG_INV_GLOBAL_L2;
flush_bits |= RADV_CMD_FLAG_INV_L2;
break;
case VK_ACCESS_COLOR_ATTACHMENT_READ_BIT:
if (flush_CB)
......@@ -2688,7 +2691,7 @@ void radv_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,
NULL);
}
static uint32_t
uint32_t
radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)
{
struct radv_cmd_state *state = &cmd_buffer->state;
......@@ -3352,7 +3355,7 @@ VkResult radv_EndCommandBuffer(
if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2;
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH | RADV_CMD_FLAG_WB_L2;
/* Make sure to sync all pending active queries at the end of
* command buffer.
......@@ -3724,6 +3727,15 @@ void radv_CmdExecuteCommands(
if (secondary->sample_positions_needed)
primary->sample_positions_needed = true;
if (!secondary->state.framebuffer &&
(primary->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)) {
/* Emit the framebuffer state from primary if secondary
* has been recorded without a framebuffer, otherwise
* fast color/depth clears can't work.
*/
radv_emit_framebuffer_state(primary);
}
primary->device->ws->cs_execute_secondary(primary->cs, secondary->cs);
......@@ -4883,20 +4895,23 @@ static void radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffe
}
static void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image, uint32_t value)
struct radv_image *image,
const VkImageSubresourceRange *range,
uint32_t value)
{
struct radv_cmd_state *state = &cmd_buffer->state;
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
state->flush_bits |= radv_clear_cmask(cmd_buffer, image, range, value);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
struct radv_image *image)
struct radv_image *image,
const VkImageSubresourceRange *range)
{
struct radv_cmd_state *state = &cmd_buffer->state;
static const uint32_t fmask_clear_values[4] = {
......@@ -4911,7 +4926,7 @@ void radv_initialize_fmask(struct radv_cmd_buffer *cmd_buffer,
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
state->flush_bits |= radv_clear_fmask(cmd_buffer, image, value);
state->flush_bits |= radv_clear_fmask(cmd_buffer, image, range, value);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
......@@ -4921,11 +4936,56 @@ void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer,
const VkImageSubresourceRange *range, uint32_t value)
{
struct radv_cmd_state *state = &cmd_buffer->state;
uint32_t level_count = radv_get_levelCount(image, range);
unsigned size = 0;
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
state->flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);