- 16 Jan, 2022 14 commits
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Doing this for ir3 required adding a struct for limits of how much base to fold in (which NTT wants as well for its case of shared vars), otherwise the later work to lower to the 1<<9 word limit would emit more instructions. The shader-db results are that sometimes the reduction in NIR instruction count results in the fewer sampler prefetches due to the shader being estimated to be shorter (dota2, nexuiz): total instructions in shared programs: 8996651 -> 8996776 (<.01%) total cat5 in shared programs: 86561 -> 86577 (0.02%) Reviewed-by:
Rob Clark <robdclark@chromium.org> Part-of: <mesa/mesa!14023>
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Saves some work in carchase and manhattan31: instructions in affected programs: 2842 -> 2818 (-0.84%) nops in affected programs: 1131 -> 1105 (-2.30%) non-nops in affected programs: 1236 -> 1238 (0.16%) mov in affected programs: 57 -> 61 (7.02%) dwords in affected programs: 2144 -> 2150 (0.28%) cat0 in affected programs: 1195 -> 1169 (-2.18%) cat1 in affected programs: 151 -> 155 (2.65%) cat2 in affected programs: 142 -> 140 (-1.41%) sstall in affected programs: 190 -> 178 (-6.32%) (ss) in affected programs: 63 -> 63 (0.00%) systall in affected programs: 532 -> 511 (-3.95%) Part-of: <mesa/mesa!14023>
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Lower to `sample_mask = 0`. Actually that implements a demote... doing discard correctly probably requires rewriting the shader control flow to insert a return where necessary... Also, possibly we should be lowering this in NIR to play nice with gl_SampleMask writes but that's a problem for when we understand the hardware better. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <mesa/mesa!14219> -
Sets the output sample mask to a given 8-bit immediate or 16-bit register. Also used to implement discards, which is my ES2 interest. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <mesa/mesa!14219> -
Compiler-controlled bit in the cmdstream. Some other magic bits are needed for sample mask writes to work properly. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io>
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The field was split up... Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io>
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What the other 31 bits are for is anyone's guess. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <mesa/mesa!14219> -
Enough bits of this packet are known that open-coding hex bytes for it is annoying. Add some XML correpsonding to what we know. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <mesa/mesa!14219> -
Alyssa Rosenzweig authored
I don't want your pesky bug report. Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <mesa/mesa!14579> -
Alyssa Rosenzweig authored
Signed-off-by:
Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <mesa/mesa!14579> -
Issue: objects[i].size is returned as '0' for all Root cause: The value of objects.size is hard coded to '0' in vlVaExportSurfaceHandle() Fix: Assigning the value by multiplying height and width of the surface Signed-off-by:
Krunal Patel <krunalkumarmukeshkumar.patel@amd.corp-partner.google.com> Reviewed-by:
Leo Liu <leo.liu@amd.com> Part-of: <mesa/mesa!14313>
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Issue: VADRMPRIMESurfaceDescriptor width and height are rounded up to macroblock size (16). Rootcause: surf->buffer's width/height are rounded up to macroblock size (16), so they shouldn't be used here. Fix: Using surf->templ's width/height instead fixes incorrect surface dimensions being sent via VADRMPRIMESurfaceDescriptor. Signed-off-by:
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The documentation[1] for the csv module specifies that we should specify newline='' when opening the output file. Without that, the module garbles the newlines, writing them as \r\r\n on Windows instead of \r\n. So let's do what the documentation says, and specify newline='' [1]: https://docs.python.org/3/library/csv.html#id3 Reviewed-by:
Eric Engestrom <eric@engestrom.ch> Part-of: <mesa/mesa!12405>
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According to RFC 4189 CSV files should be encoded using CRLF newlines, not LF. This helps compatibility with tools, like python's csv module, who always uses CRLF. While we're at it, normalize the one CSV that was CRLF in-repo to LF, and let git do the newline-normalization when needed instead. Reviewed-by:
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- 15 Jan, 2022 18 commits
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By software ABI, a blend shader is permitted to clobber registers R0-R15. The scheduler needs to be aware of this, to avoid moving a write to one of these registers past the BLEND itself. Otherwise the schedule is invalid. This bug affects GLES3.0, but is rare enough in practice that we had missed it. It requires a fragment shader to write to multiple render targets with attached blend shaders, and have temporaries register allocated to R0-R15 that are not read by the blend shader, but are sunk past the BLEND instruction by the scheduler. Prevents a regression when switching boolean representations on: dEQP-GLES31.functional.shaders.builtin_functions.integer.uaddcarry.uvec4_lowp_fragment Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <!14577> -
Alyssa Rosenzweig authored
Although Bifrost clause packing and register assignment is tricky, the relevant code is by now extensively tested, and there's no remaining reverse-engineering here. So disassembling verbosely just adds tons of noise to pandecode without increasing the useful information. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Suggested-by: Icecream95 <ixn@disroot.org> Part-of: <!14543>
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Alyssa Rosenzweig authored
It's already printed in the RSD itself, no need to print it out-of-band a second time. Removes noise in the pandecode. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <!14543> -
Alyssa Rosenzweig authored
It's a pointer to a thread storage descriptor, not a framebuffer descriptor. Unlike Midgard, these don't have to alias. The FBD pointer was unused anyway, so remove it to reduce noise in pandecode dumps. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <!14543> -
Alyssa Rosenzweig authored
Instead of incorrectly falling down the Bifrost path. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <!14543> -
Alyssa Rosenzweig authored
Add a helper to dump all mapped GPU memory. This is a blunt, seldom useful instrument ... but when it /is/ useful it's your only option. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <!14543> -
Alyssa Rosenzweig authored
I think I originally wrote this for Asahi? Should probably be moved to util/... Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <!14543> -
Alyssa Rosenzweig authored
Rather than emulating page tables, poorly, with a hash table, use a red-black tree and store the intervals directly. This is deterministic instead of probabilistic, attaining O(log n) performance for n mapped intervals which is good enough. Unlike the hash table approach, this allows us to iterate intervals easily. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <!14543> -
Alyssa Rosenzweig authored
Helpful for contextualizing fault pointers. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <!14543> -
Alyssa Rosenzweig authored
This has never been meaningful. Signed-off-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <!14543> -
Reviewed-by:
Emma Anholt <emma@anholt.net> Part-of: <!14545>
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meta was the last user. Reviewed-by:
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- 14 Jan, 2022 8 commits
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For cmdstream traces from newer devices, we need to identify the gpu based on chip-id. Signed-off-by:
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A rule with executable_regexp tag would match every executable without this fix and force_glsl_extensions_warn would be always set to true which breaks some dEQP tests. Fixes: 5740ac37 ("xmlconfig: Add static driconfig support") Reviewed-by:
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The switch statement in anv_descriptor_data_for_type() shows that this field isn't used on SKL+. On XeHP, this avoids assert failures by preventing isl_surf_fill_image_param() from being called. That function doesn't expect Tile4 surfaces. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <!14546> -
Reviewed-by:
Rohan Garg <rohan.garg@intel.com> Acked-by:
Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <!13996> -
v2: Fixup gpu_id computation, use minor of /dev/dri/* % 128 since we don't know whether we get card0 or renderD128 for instance. (Lionel) Signed-off-by:Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com> (v1)
Acked-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <!13996> -
Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <!13996> -
Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <!13996> -
v2: Increase custom stall data (Felix) Fixup build (Felix) v3: Add API enum (Rohan) Fixup old comment (Rohan) Signed-off-by:Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <!13996>
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