Skip to content
  • Rob Clark's avatar
    WIP: freedreno: Add 'cachedlinear' debug flag · a17c739d
    Rob Clark authored
    Normally we expect bo's to be accessed more by the GPU than the CPU
    (other than special cases like staging transfer buffers).  But this
    isn't the case for dEQP/piglit.  Add a special flag to force linear
    resources to be allocated cached to speed up CPU access to buffers
    that would normally be allocated write-combine.
    a17c739d