- Sep 24, 2019
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Andreas Baierl authored
Some ops can't deal with abs sources directly, so we have to lower the abs modifier. Lower abs like sqrt(mul(x, x)). This is what the blob does and we pass some more piglit tests. This ppir lowering pass is executed at the very end when lowering of all the other alu instructions is already done but before lowering the consts. Signed-off-by: Andreas Baierl <ichgeh@imkreisrum.de>
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Connor Abbott authored
There are 64 physical registers so the shift must be 64 bits. Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
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Connor Abbott authored
The scheduler doesn't expect them. To do this, I had to refactor the registration part of gpir_node_create_dest() to be separate from creating and inserting the node, since the last two now aren't done when handling moves. This adds more code but creates the possibility of automatically inserting input dependencies when inserting nodes, similar to what's done in NIR with the use-def lists (this isn't done yet). Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
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Connor Abbott authored
We guarantee that a complex1 op is always used by postlog2 directly by rewriting the postlog2 op to be a move when there would be a move inserted between them. But we weren't doing this in all circumstances where there might be a move. Move the logic to place_move() so that it always happens. Fixes a few log tests that happened to start failing due to changes in the register allocator leading to a different scheduling order. Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
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Connor Abbott authored
This commit adds the framework for cross-basic-block register allocation. Like ARM's compiler, we assume that the value registers aren't usable across branches, which means we have to use physical registers to store any value that crosses a basic block. There are three parts to this: 1. When translating from NIR, we rely on the NIR out-of-ssa pass to coalesce values into registers. We insert store_reg instructions for values used in more than one basic block, and load_reg instructions for values not defined in the same basic block (or defined after their use, for loops). So by the time we've translated out of NIR we've already split things into values (which are only used in the same basic block) and registers (which are only used in different basic blocks than where they're defined). 2. We allocate the registers at the same time that we allocate the values, before the final scheduler. Unlike the values, where the assigned color is fake, we assign the actual physical index & component to physregs at this stage. load_reg and store_reg are treated as moves in the allocator and when creating write-after-read dependencies. 3. Finally, in the main scheduler we have to avoid overwriting existing live physregs when spilling. First, we have to tell the scheduler which physical registers are live at the end of each block, to avoid overwriting those. If a register is only live at the beginning, we can reuse it for spilling after the last original use in the final program happens, i.e. before any original use is scheduled, but we have to be careful to add the proper dependencies so that the spill write is scheduled before the original reads. To handle this we repurpose reg_link for uses to be used by the scheduler. A few register-related things copied over from NIR or from other drivers can be dropped. Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
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Connor Abbott authored
Because branch conditions have to be in the pass slot, there is no unconditional branch, and realistically the pass slot has to contain a move when branching (there's nothing it does that would be useful for operating on booleans, so we can't use it for anything when computing the branch condition), we put the branch instruction in the pass slot and at codegen time turn it into a move of the branch condition. This means that it doesn't have to be special-cased like store instructions are in the scheduler. Because of this decision we can remove the half-implemented BRANCH codegen slot. Finally, we (ab)use the existing schedule_first mechanism to make sure that branches are always last in the basic block. Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
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Connor Abbott authored
When picking a node to be scheduled, we try to schedule its children as well. But we shouldn't try to schedule nodes which only have a fake dependency on the original node, since this isn't the point of scheduling children at the same time and can break some expectations of the rest of the code. Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
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Connor Abbott authored
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
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Adam Jackson authored
This is the GLX counterpart to EGL_KHR_no_config_context. Contexts may now be created without reference to an fbconfig, in which case it is treated as compatible with any fbconfig (and thus any GLX drawable). Khronos: https://github.com/KhronosGroup/OpenGL-Registry/pull/102 Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
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Adam Jackson authored
Somewhat terrifyingly, we never sent this for direct contexts, which means the server never knew the context/drawable bindings. To handle this sanely, pull the request code up out of the indirect backend, and rewrite the context switch path to call it as appropriate. This attempts to preserve the existing behavior of not calling unbind() on the context if its refcount would not drop to zero. Of course, you can't just do this indiscriminately, because this is GLX and extant X servers have bugs and everything is terrible. To wit: - For 1.20.x prior to 1.20.6, you can bind a direct context once, but the second time you try to modify the context's binding you will get GLXBadContextTag. This includes unbinding the context. And "deleting" the context will leak memory, because it will still appear to be current. - For 1.19 and earlier, glXMakeCurrent(dpy, None, ctx) should be legal for GL 3.0+ contexts, but the server will throw BadMatch. To guard against this, we only send the request for indirect contexts unless the server is known good, and only mention one context at a time in such a request; if switching between contexts, we first unbind the old, and then bind the new. Note that the second VendorRelease() version is to catch XFree86 4.x and Xorg [67].x, which almost certainly have the above bugs. Other servers might report different version numbers here, but we can't do direct rendering against them, so this should be safe. Fixes glx-make-context, glx-multi-window-single-context and glx-query-drawable-glx_fbconfig_id-window. Sufficiently old piglit will regress on glx-make-glxdrawable-current (throwing BadMatch), which is fixed by piglit!116.
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Adam Jackson authored
Only relevant for indirect contexts, so let's get that code out of the common path.
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- Sep 23, 2019
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Kenneth Graunke authored
From the MEDIA_VFE_STATE docs: "Starting with this configuration, the Maximum Number of Threads must be set to (#EU * 8) for GPGPU dispatches. Although there are only 7 threads per EU in the configuration, the FFTID is calculated as if there are 8 threads per EU, which in turn requires a larger amount of Scratch Space to be allocated by the driver." It's pretty clear that we need to increase this for scratch address calculations, because the FFTID has a certain bit-pattern. The quote above seems to indicate that we should increase the actual thread count programmed in MEDIA_VFE_STATE as well, but we think the intention is to only bump the scratch space. Fixes GPU hangs in Bioshock Infinite and Synmark's CSDof on Icelake 8x8. Fixes: 5ac804bd ("intel: Add a preliminary device for Ice Lake") Reviewed-by: Matt Turner <mattst88@gmail.com>
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Kenneth Graunke authored
This reverts commit 729de148. It turns out that, although the register is in the logical context, it isn't whitelisted, so we can't actually write it from userspace batch buffers. The write just becomes a noop, which is why we saw no performance changes. I manually whitelisted it, and still observed no performance gains, but it did regress KHR-GL46.texture_cube_map_array.color_depth_attachments on the iris driver. So we might need to fix something before enabling this. To prevent it randomly getting turned on should the kernel ever whitelist this register, we revert the patch for now.
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Faith Ekstrand authored
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
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Kenneth Graunke authored
'α' has never appeared in any genxml files, so there's no need to replace it with the word "alpha". Reviewed-by: Eric Anholt <eric@anholt.net>
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Kenneth Graunke authored
'α' has never appeared in any genxml files, so there's no need to replace it with the word "alpha". Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
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Use VPC_SO_OVERRIDE to control whether we do streamout in binning or draw pass. Normally we want to do streamout in binning pass, except when there is a single tile and binning passed is skipped. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
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We could bit doing streamout from binning pass. In this case we want to use the full VS which doesn't have (potentially streamed out) varyings stripped out. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
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Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Eric Anholt <eric@anholt.net> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
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Marek Olšák authored
This fixes VAAPI. Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
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Marek Olšák authored
This fixes some dEQP tests. Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
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Marek Olšák authored
Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
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Marek Olšák authored
This caused a failure in NIR validation. Reviewed-by: Connor Abbott <cwabbott0@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net>
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Marek Olšák authored
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
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Marek Olšák authored
It confuses radeonsi. Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
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Marek Olšák authored
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
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Sonny Jiang authored
v2: cleanup Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Signed-off-by: Marek Olšák <marek.olsak@amd.com> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
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Marek Olšák authored
PCI IDs for amdgpu will be removed from Mesa. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
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Marek Olšák authored
Cc: 19.2 <mesa-stable@lists.freedesktop.org> Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
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Marek Olšák authored
trivial and urgent Cc: 19.2 <mesa-stable@lists.freedesktop.org>
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Eric Engestrom authored
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com> Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
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Faith Ekstrand authored
In a3268599, I attempted to fix nir_repair_ssa for unreachable blocks. However, that commit missed the possibility that the use is in a block which, itself, is unreachable. In this case, we can end up in an infinite loop trying to replace a def with itself. Even though a no-op replacement is a fine operation, it keeps extending the end of the uses list as we're walking it. Instead of explicitly checking for the group of conditions, just check if the phi builder gives us a different def. That's guaranteed to be 100% reliable and, while it lacks symmetry with the is_valid checks, should be more reliable. Fixes: a3268599 "nir/repair_ssa: Repair dominance for unreachable..." Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
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Daniel Schürmann authored
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
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Karol Herbst authored
Signed-off-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Rhys Kidd <rhyskidd@gmail.com>
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Karol Herbst authored
Signed-off-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Rhys Kidd <rhyskidd@gmail.com>
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Erico Nunes authored
pipe->clear() is not called for partial clears, which mesa emulates by drawing a quad. Furthermore, drivers should not use rasterizer state information for scissor information (which was being used to handle the partial clears). So, remove the partial clear support since it was not supposed to be handled by pipe->clear() anyway. This fixes issues with clearing after switching to different sized framebuffers. Signed-off-by: Erico Nunes <nunes.erico@gmail.com> Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Qiang Yu <yuq825@gmail.com>
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Boris Brezillon authored
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
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Boris Brezillon authored
->padded_count should be large enough to cover all vertices pointed by the index array. Use the local vertex_count variable that contains the updated vertex_count value for the indexed draw case. Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
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fixes "sorry, unimplemented: non-trivial designated initializers not supported" Fixes: deb04adf ("clover: add support for passing kernels as nir to the driver") Signed-off-by: Karol Herbst <kherbst@redhat.com> Reviewed-by: Eric Engestrom <eric@engestrom.ch>
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Kenneth Graunke authored
Incomplete attachments don't have an associated pipe_surface, so this would crash. Fixes a WebGL conformance test that uses incomplete attachments: https://www.khronos.org/registry/webgl/sdk/tests/conformance2/renderbuffers/invalidate-framebuffer.html?webglVersion=2&quiet=0&quick=1 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111756 Reviewed-By: Tapani Pälli <tapani.palli@intel.com>
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