1. 20 Jul, 2015 4 commits
  2. 18 Jul, 2015 11 commits
    • Ilia Mirkin's avatar
      gm107/ir: fix indirect txq emission · 8c8a71f0
      Ilia Mirkin authored
      
      
      Signed-off-by: Ilia Mirkin's avatarIlia Mirkin <imirkin@alum.mit.edu>
      Cc: mesa-stable@lists.freedesktop.org
      8c8a71f0
    • Ilia Mirkin's avatar
      nvc0/ir: don't worry about sampler in txq handling · 346ce0b9
      Ilia Mirkin authored
      
      
      There's no need to deal with samplers for texture size queries. That
      code also was accidentally setting an invalid sIndirectSrc position, but
      it can now just be removed.
      
      Signed-off-by: Ilia Mirkin's avatarIlia Mirkin <imirkin@alum.mit.edu>
      Cc: mesa-stable@lists.freedesktop.org
      346ce0b9
    • Ilia Mirkin's avatar
      nvc0/ir: fix txq on indirect samplers · 20e484af
      Ilia Mirkin authored
      
      
      Signed-off-by: Ilia Mirkin's avatarIlia Mirkin <imirkin@alum.mit.edu>
      Cc: mesa-stable@lists.freedesktop.org
      20e484af
    • Abdiel Janulgue's avatar
      i965: Disable resource streamer in BLORP · 670914ea
      Abdiel Janulgue authored
      
      
      Switch off hardware-generated binding tables and gather push
      constants in the blorp. Blorp requires only a minimal set of
      simple constants. There is no need for the extra complexity
      to program a gather table entry into the pipeline.
      
      Cc: kenneth@whitecape.org
      Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
      Signed-off-by: default avatarAbdiel Janulgue <abdiel.janulgue@linux.intel.com>
      670914ea
    • Abdiel Janulgue's avatar
      i965: Upload binding tables in hw-generated binding table format. · fc65b6eb
      Abdiel Janulgue authored
      
      
      When hardware-generated binding tables are enabled, use the hw-generated
      binding table format when uploading binding table state.
      
      Normally, the CS will will just consume the binding table pointer commands
      as pipelined state. When the RS is enabled however, the RS flushes whatever
      edited surface state entries of our on-chip binding table to the binding
      table pool before passing the command on to the CS.
      
      Note that the the binding table pointer offset is relative to the binding table
      pool base address when resource streamer instead of the surface state base address.
      
      v2: Fix possible buffer overflow when allocating a chunk out of the
          hw-binding table pool (Ken).
      v3: Remove extra newline and add missing brace around if-statement (Matt).
      v4: Fix broken INTEL_DEBUG=shader_time for hw-generated binding tables.
          Document PRM WaStateBindingTableOverfetch workaround.
      
      Cc: kenneth@whitecape.org
      Cc: mattst88@gmail.com
      Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
      Signed-off-by: default avatarAbdiel Janulgue <abdiel.janulgue@linux.intel.com>
      fc65b6eb
    • Abdiel Janulgue's avatar
      i965: Implement interface to edit binding table entries · 2133980b
      Abdiel Janulgue authored
      
      
      Unlike normal software binding tables where the driver has to manually
      generate and fill a binding table array which are then uploaded to the
      hardware, the resource streamer instead presents the driver with an option
      to fill out slots for individual binding table indices. The hardware
      accumulates the state for these combined edits which it then automatically
      flushes to a binding table pool when the binding table pointer state
      command is invoked.
      
      v2: Clarify binding table edit bit aligment (Topi).
      v3: Make comments and function names more clearer (Ken).
      
      Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
      Signed-off-by: default avatarAbdiel Janulgue <abdiel.janulgue@linux.intel.com>
      2133980b
    • Abdiel Janulgue's avatar
      i965: Enable hardware-generated binding tables on render path. · 19075648
      Abdiel Janulgue authored
      
      
      This patch implements the binding table enable command which is also
      used to allocate a binding table pool where where hardware-generated
      binding table entries are flushed into. Each binding table offset in
      the binding table pool is unique per each shader stage that are
      enabled within a batch.
      
      Also insert the required brw_tracked_state objects to enable
      hw-generated binding tables in normal render path.
      
      v2: - Use MOCS in binding table pool alloc for GEN8
          - Fix spurious offset when allocating binding table pool entry
            and start from zero instead.
      v3: - Include GEN8 fix for spurious offset above.
      v4: - Fixup wrong packet length in enable/disable hw-binding table
            for GEN8 (Ville).
          - Don't invoke HW-binding table disable command when we dont
            have resource streamer (Chris).
      v5: - Reorder the state cache invalidate flush so it happens in-between
            enabling hw-generated binding tables and the previous sw-binding
            table GPU state (Chris).
      v6: - Do the same fix in v5 for gen7_disable_hw_binding_tables().
          - Adhere to coding guidelines and make comments more informative.
      
      Cc: kenneth@whitecape.org
      Cc: syrjala@sci.fi
      Cc: chris@chris-wilson.co.uk
      Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
      Signed-off-by: default avatarAbdiel Janulgue <abdiel.janulgue@linux.intel.com>
      19075648
    • Abdiel Janulgue's avatar
      i965: Enable resource streamer for the batchbuffer · 090529af
      Abdiel Janulgue authored
      
      
      Check first if the hardware and kernel supports resource streamer. If this
      is allowed, tell the kernel to enable the resource streamer enable bit on
      MI_BATCHBUFFER_START by specifying I915_EXEC_RESOURCE_STREAMER
      execbuffer flags.
      
      v2: - Use new I915_PARAM_HAS_RESOURCE_STREAMER ioctl to check if kernel
            supports RS (Ken).
          - Add brw_device_info::has_resource_streamer and toggle it for
            Haswell, Broadwell, Cherryview, Skylake, and Broxton (Ken).
      v3: - Update I915_PARAM_HAS_RESOURCE_STREAMER to match updated kernel.
      v4: - Always inspect the getparam.value (Chris Wilson).
      v5: - Fold redundant devinfo->has_resource_streamer check in context create
            into init screen.
      
      Cc: kenneth@whitecape.org
      Cc: chris@chris-wilson.co.uk
      Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
      Signed-off-by: default avatarAbdiel Janulgue <abdiel.janulgue@linux.intel.com>
      090529af
    • Abdiel Janulgue's avatar
      i965: Define HW-binding table and resource streamer control opcodes · ccf9598a
      Abdiel Janulgue authored
      
      
      v2: Use macros for HW binding table edits (Topi)
      v3: Add Broadwell support.
      v4: Make hardware binding table bit definitions even more clearer (Ken)
      
      Cc: kenneth@whitecape.org
      Reviewed-by: Topi Pohjolainen's avatarTopi Pohjolainen <topi.pohjolainen@intel.com>
      Reviewed-by: Kenneth Graunke's avatarKenneth Graunke <kenneth@whitecape.org>
      Signed-off-by: default avatarAbdiel Janulgue <abdiel.janulgue@linux.intel.com>
      ccf9598a
    • Emma Anholt's avatar
      vc4: Switch to using a separate ioctl for making shaders. · ff7896a3
      Emma Anholt authored
      This gives the kernel a chance to validate and lock down the data,
      without having to deal with mmap zapping.
      
      With this, GLBenchmark stops on a texture relocations, because we'd
      recycled a shader BO as another shader and failed to revalidate, since we
      weren't clearing the cached validation state on mmap faults.
      ff7896a3
    • Roland Scheidegger's avatar
      mesa: fix up some texture error checks · e42cfe5d
      Roland Scheidegger authored
      
      
      In particular, we were incorrectly accepting s3tc (and lots of others)
      for CompressedTexSubImage3D (but not CompressedTexImage3D) calls with 3d
      targets. At this time, the only allowed formats for these calls are the
      bptc ones, since none of the specific extensions allow it (astc hdr would).
      Also, fix up a bug in _mesa_target_can_be_compressed - 3d target needs to
      be allowed for bptc formats.
      
      Reviewed-by: Brian Paul's avatarBrian Paul <brianp@vmware.com>
      e42cfe5d
  3. 17 Jul, 2015 15 commits
  4. 16 Jul, 2015 10 commits