Commit 9c64cb80 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

nvc0: enable support for maxwell boards


Signed-off-by: Ben Skeggs's avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: Ilia Mirkin's avatarIlia Mirkin <imirkin@alum.mit.edu>
parent d548d47e
......@@ -329,7 +329,8 @@ nvc0_create(struct pipe_screen *pscreen, void *priv)
flags = NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR;
BCTX_REFN_bo(nvc0->bufctx_3d, SCREEN, flags, screen->poly_cache);
if (screen->poly_cache)
BCTX_REFN_bo(nvc0->bufctx_3d, SCREEN, flags, screen->poly_cache);
if (screen->compute)
BCTX_REFN_bo(nvc0->bufctx_cp, CP_SCREEN, flags, screen->tls);
......
......@@ -435,8 +435,10 @@ nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
BEGIN_NVC0(push, SUBC_3D(0x0de8), 1);
PUSH_DATA (push, 1);
BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
PUSH_DATA (push, 0);
if (obj_class < GM107_3D_CLASS) {
BEGIN_NVC0(push, SUBC_3D(0x12ac), 1);
PUSH_DATA (push, 0);
}
BEGIN_NVC0(push, SUBC_3D(0x0218), 1);
PUSH_DATA (push, 0x10);
BEGIN_NVC0(push, SUBC_3D(0x10fc), 1);
......@@ -464,12 +466,15 @@ nvc0_magic_3d_init(struct nouveau_pushbuf *push, uint16_t obj_class)
PUSH_DATA (push, 1);
BEGIN_NVC0(push, SUBC_3D(0x19c0), 1);
PUSH_DATA (push, 1);
BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
PUSH_DATA (push, 3);
if (obj_class >= NVE4_3D_CLASS) {
BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
PUSH_DATA (push, 1);
if (obj_class < GM107_3D_CLASS) {
BEGIN_NVC0(push, SUBC_3D(0x075c), 1);
PUSH_DATA (push, 3);
if (obj_class >= NVE4_3D_CLASS) {
BEGIN_NVC0(push, SUBC_3D(0x07fc), 1);
PUSH_DATA (push, 1);
}
}
/* TODO: find out what software methods 0x1528, 0x1280 and (on nve4) 0x02dc
......@@ -518,6 +523,8 @@ nvc0_screen_init_compute(struct nvc0_screen *screen)
case 0xf0:
case 0x100:
return nve4_screen_compute_setup(screen, screen->base.pushbuf);
case 0x110:
return 0;
default:
return -1;
}
......@@ -579,6 +586,7 @@ nvc0_screen_create(struct nouveau_device *dev)
case 0xe0:
case 0xf0:
case 0x100:
case 0x110:
break;
default:
return NULL;
......@@ -635,6 +643,7 @@ nvc0_screen_create(struct nouveau_device *dev)
switch (dev->chipset & ~0xf) {
case 0x110:
case 0x100:
case 0xf0:
obj_class = NVF0_P2MF_CLASS;
......@@ -858,15 +867,17 @@ nvc0_screen_create(struct nouveau_device *dev)
BEGIN_NVC0(push, NVC0_3D(LOCAL_BASE), 1);
PUSH_DATA (push, 0);
ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
&screen->poly_cache);
if (ret)
goto fail;
if (screen->eng3d->oclass < GM107_3D_CLASS) {
ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 20, NULL,
&screen->poly_cache);
if (ret)
goto fail;
BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->poly_cache->offset);
PUSH_DATA (push, screen->poly_cache->offset);
PUSH_DATA (push, 3);
BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->poly_cache->offset);
PUSH_DATA (push, screen->poly_cache->offset);
PUSH_DATA (push, 3);
}
ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 17, 1 << 17, NULL,
&screen->txc);
......
......@@ -543,9 +543,23 @@ nvc0_blitter_make_vp(struct nvc0_blitter *blit)
0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
0x00001de7, 0x80000000, /* exit */
};
static const uint32_t code_gm107[] =
{
0xfc0007e0, 0x001f8000, /* sched 0x7e0 0x7e0 0x7e0 */
0x0807ff04, 0xefd8ff80, /* ld b64 $r4 a[0x80] 0x0 */
0x0907ff00, 0xefd97f80, /* ld b96 $r0 a[0x90] 0x0 */
0x0707ff04, 0xeff0ff80, /* st b64 a[0x70] $r4 0x0 */
0xfc0007e0, 0x00000000, /* sched 0x7e0 0x7e0 0x0 */
0x0807ff00, 0xeff17f80, /* st b96 a[0x80] $r0 0x0 */
0x0007000f, 0xe3000000, /* exit */
};
blit->vp.type = PIPE_SHADER_VERTEX;
blit->vp.translated = TRUE;
if (blit->screen->base.class_3d >= GM107_3D_CLASS) {
blit->vp.code = (uint32_t *)code_gm107; /* const_cast */
blit->vp.code_size = sizeof(code_gm107);
} else
if (blit->screen->base.class_3d >= NVE4_3D_CLASS) {
blit->vp.code = (uint32_t *)code_nve4; /* const_cast */
blit->vp.code_size = sizeof(code_nve4);
......
......@@ -771,7 +771,8 @@ nvc0_draw_stream_output(struct nvc0_context *nvc0,
PUSH_SPACE(push, 2);
IMMED_NVC0(push, NVC0_3D(SERIALIZE), 0);
nvc0_query_fifo_wait(push, so->pq);
IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
NOUVEAU_DRV_STAT(&nvc0->screen->base, gpu_serialize_count, 1);
}
......@@ -859,7 +860,8 @@ nvc0_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info)
nvc0->base.vbo_dirty = TRUE;
if (nvc0->base.vbo_dirty) {
IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
IMMED_NVC0(push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
nvc0->base.vbo_dirty = FALSE;
}
......
......@@ -488,7 +488,8 @@ nvc0_push_vbo(struct nvc0_context *nvc0, const struct pipe_draw_info *info)
if (unlikely(ctx.need_vertex_id))
nvc0_push_upload_vertex_ids(&ctx, nvc0, info);
IMMED_NVC0(ctx.push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
if (nvc0->screen->eng3d->oclass < GM107_3D_CLASS)
IMMED_NVC0(ctx.push, NVC0_3D(VERTEX_ARRAY_FLUSH), 0);
BEGIN_NVC0(ctx.push, NVC0_3D(VERTEX_BEGIN_GL), 1);
PUSH_DATA (ctx.push, prim);
switch (index_size) {
......
......@@ -96,6 +96,7 @@ nouveau_drm_screen_create(int fd)
case 0xe0:
case 0xf0:
case 0x100:
case 0x110:
init = nvc0_screen_create;
break;
default:
......
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