src/amd/common/ac_gpu_info.c

@@ -1456,6 +1456,7 @@ bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
    info->gfx12_supports_dcc_write_compress_disable = info->gfx_level >= GFX12 && info->drm_minor >= 60;
 
    info->has_stable_pstate = info->drm_minor >= 45;
+   info->has_explicit_sync_vm_ops = info->drm_minor >= 60;
 
    if (info->gfx_level >= GFX12) {
       /* Gfx12 doesn't use pc_lines and pbb_max_alloc_count. */
@@ -1996,6 +1997,7 @@ void ac_print_gpu_info(const struct radeon_info *info, FILE *f)
    fprintf(f, "    has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
    fprintf(f, "    has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
    fprintf(f, "    has_stable_pstate = %u\n", info->has_stable_pstate);
+   fprintf(f, "    has_explicit_sync_vm_ops = %u\n", info->has_explicit_sync_vm_ops);
    fprintf(f, "    has_gang_submit = %u\n", info->has_gang_submit);
    fprintf(f, "    has_gpuvm_fault_query = %u\n", info->has_gpuvm_fault_query);
    fprintf(f, "    register_shadowing_required = %u\n", info->register_shadowing_required);

src/amd/common/ac_gpu_info.h

@@ -238,6 +238,7 @@ struct radeon_info {
    bool has_gpuvm_fault_query;
    bool has_pcie_bandwidth_info;
    bool has_stable_pstate;
+   bool has_explicit_sync_vm_ops;
    /* Whether SR-IOV is enabled or amdgpu.mcbp=1 was set on the kernel command line. */
    bool register_shadowing_required;
    bool has_tmz_support;

src/amd/vulkan/radv_buffer.c

@@ -274,14 +274,15 @@ radv_bo_destroy(struct radv_device *device, struct vk_object_base *object, struc
 
 VkResult
 radv_bo_virtual_bind(struct radv_device *device, struct vk_object_base *object, struct radeon_winsys_bo *parent,
-                     uint64_t offset, uint64_t size, struct radeon_winsys_bo *bo, uint64_t bo_offset)
+                     uint64_t offset, uint64_t size, struct radeon_winsys_bo *bo, uint64_t bo_offset, uint32_t wait_count,
+                     const struct vk_sync_wait *waits)
 {
    struct radv_physical_device *pdev = radv_device_physical(device);
    struct radv_instance *instance = radv_physical_device_instance(pdev);
    struct radeon_winsys *ws = device->ws;
    VkResult result;
 
-   result = ws->buffer_virtual_bind(ws, parent, offset, size, bo, bo_offset);
+   result = ws->buffer_virtual_bind(ws, parent, offset, size, bo, bo_offset, wait_count, waits);
    if (result != VK_SUCCESS)
       return result;
 

src/amd/vulkan/radv_buffer.h

@@ -37,7 +37,8 @@ VkResult radv_bo_create(struct radv_device *device, struct vk_object_base *objec
 
 VkResult radv_bo_virtual_bind(struct radv_device *device, struct vk_object_base *object,
                               struct radeon_winsys_bo *parent, uint64_t offset, uint64_t size,
-                              struct radeon_winsys_bo *bo, uint64_t bo_offset);
+                              struct radeon_winsys_bo *bo, uint64_t bo_offset, uint32_t wait_count,
+                              const struct vk_sync_wait *waits);
 
 void radv_bo_destroy(struct radv_device *device, struct vk_object_base *object, struct radeon_winsys_bo *bo);
 

src/amd/vulkan/radv_radeon_winsys.h

@@ -261,7 +261,8 @@ struct radeon_winsys {
    void (*buffer_get_metadata)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, struct radeon_bo_metadata *md);
 
    VkResult (*buffer_virtual_bind)(struct radeon_winsys *ws, struct radeon_winsys_bo *parent, uint64_t offset,
-                                   uint64_t size, struct radeon_winsys_bo *bo, uint64_t bo_offset);
+                                   uint64_t size, struct radeon_winsys_bo *bo, uint64_t bo_offset, uint32_t wait_count,
+                                   const struct vk_sync_wait *waits);
 
    VkResult (*buffer_make_resident)(struct radeon_winsys *ws, struct radeon_winsys_bo *bo, bool resident);
 

src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c

@@ -29,12 +29,36 @@
 #include "util/u_math.h"
 #include "util/u_memory.h"
 
+#include "vk_drm_syncobj.h"
+#include "vk_sync_dummy.h"
+
 static void radv_amdgpu_winsys_bo_destroy(struct radeon_winsys *_ws, struct radeon_winsys_bo *_bo);
 
 static int
 radv_amdgpu_bo_va_op(struct radv_amdgpu_winsys *ws, uint32_t bo_handle, uint64_t offset, uint64_t size, uint64_t addr,
-                     uint32_t bo_flags, uint64_t internal_flags, uint32_t ops)
+                     uint32_t bo_flags, uint64_t internal_flags, uint32_t ops, uint32_t wait_count,
+                     const struct vk_sync_wait *waits)
 {
+   uint64_t wait_idx = 0;
+
+   STACK_ARRAY(uint64_t, wait_points, wait_count);
+   STACK_ARRAY(uint32_t, wait_syncobj, wait_count);
+
+   if (!wait_points || !wait_syncobj)
+      return -ENOMEM;
+
+   if (ws->info.has_explicit_sync_vm_ops) {
+      for (uint32_t i = 0; i < wait_count; ++i) {
+         if (waits[i].sync->type == &vk_sync_dummy_type)
+            continue;
+
+         assert(waits[i].sync->type == &ws->syncobj_sync_type);
+         wait_syncobj[wait_idx] = ((struct vk_drm_syncobj *)waits[i].sync)->syncobj;
+         wait_points[wait_idx] = waits[i].wait_value;
+         ++wait_idx;
+      }
+   }
+
    uint64_t flags = internal_flags;
    if (bo_handle) {
       flags = AMDGPU_VM_PAGE_READABLE | AMDGPU_VM_PAGE_EXECUTABLE;
@@ -48,7 +72,11 @@ radv_amdgpu_bo_va_op(struct radv_amdgpu_winsys *ws, uint32_t bo_handle, uint64_t
 
    size = align64(size, getpagesize());
 
-   return ac_drm_bo_va_op_raw(ws->dev, bo_handle, offset, size, addr, flags, ops);
+   if (ws->info.has_explicit_sync_vm_ops)
+      return ac_drm_bo_va_op_raw2(ws->dev, bo_handle, offset, size, addr, flags, ops, 0, 0, wait_idx,
+                                  (uint64_t)wait_syncobj);
+   else
+      return ac_drm_bo_va_op_raw(ws->dev, bo_handle, offset, size, addr, flags, ops);
 }
 
 static int
@@ -124,7 +152,8 @@ radv_amdgpu_log_va_op(struct radv_amdgpu_winsys *ws,
 
 static VkResult
 radv_amdgpu_winsys_bo_virtual_bind(struct radeon_winsys *_ws, struct radeon_winsys_bo *_parent, uint64_t offset,
-                                   uint64_t size, struct radeon_winsys_bo *_bo, uint64_t bo_offset)
+                                   uint64_t size, struct radeon_winsys_bo *_bo, uint64_t bo_offset, uint32_t wait_count,
+                                   const struct vk_sync_wait *waits)
 {
    struct radv_amdgpu_winsys *ws = radv_amdgpu_winsys(_ws);
    struct radv_amdgpu_winsys_bo *parent = (struct radv_amdgpu_winsys_bo *)_parent;
@@ -143,10 +172,12 @@ radv_amdgpu_winsys_bo_virtual_bind(struct radeon_winsys *_ws, struct radeon_wins
     */
    if (bo) {
       r =
-         radv_amdgpu_bo_va_op(ws, bo->bo_handle, bo_offset, size, parent->base.va + offset, 0, 0, AMDGPU_VA_OP_REPLACE);
+         radv_amdgpu_bo_va_op(ws, bo->bo_handle, bo_offset, size, parent->base.va + offset, 0, 0, AMDGPU_VA_OP_REPLACE,
+                               wait_count, waits);
       radv_amdgpu_log_va_op(ws, bo, bo_offset, size, parent->base.va + offset);
    } else {
-      r = radv_amdgpu_bo_va_op(ws, 0, 0, size, parent->base.va + offset, 0, AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_REPLACE);
+      r = radv_amdgpu_bo_va_op(ws, 0, 0, size, parent->base.va + offset, 0, AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_REPLACE,
+                               wait_count, waits);
       radv_amdgpu_log_va_op(ws, NULL, 0, size, parent->base.va + offset);
    }
 
@@ -340,7 +371,7 @@ radv_amdgpu_winsys_bo_destroy(struct radeon_winsys *_ws, struct radeon_winsys_bo
       int r;
 
       /* Clear mappings of this PRT VA region. */
-      r = radv_amdgpu_bo_va_op(ws, 0, 0, bo->base.size, bo->base.va, 0, 0, AMDGPU_VA_OP_CLEAR);
+      r = radv_amdgpu_bo_va_op(ws, 0, 0, bo->base.size, bo->base.va, 0, 0, AMDGPU_VA_OP_CLEAR, 0, NULL);
       if (r) {
          fprintf(stderr, "radv/amdgpu: Failed to clear a PRT VA region (%d).\n", r);
       }
@@ -354,7 +385,7 @@ radv_amdgpu_winsys_bo_destroy(struct radeon_winsys *_ws, struct radeon_winsys_bo
 
       if (ws->debug_all_bos)
          radv_amdgpu_global_bo_list_del(ws, bo);
-      radv_amdgpu_bo_va_op(ws, bo->bo_handle, 0, bo->base.size, bo->base.va, 0, 0, AMDGPU_VA_OP_UNMAP);
+      radv_amdgpu_bo_va_op(ws, bo->bo_handle, 0, bo->base.size, bo->base.va, 0, 0, AMDGPU_VA_OP_UNMAP, 0, NULL);
       ac_drm_bo_free(ws->dev, bo->bo);
    }
 
@@ -436,7 +467,7 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws, uint64_t size, unsigned
       bo->ranges[0].bo_offset = 0;
 
       /* Reserve a PRT VA region. */
-      r = radv_amdgpu_bo_va_op(ws, 0, 0, size, bo->base.va, 0, AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_MAP);
+      r = radv_amdgpu_bo_va_op(ws, 0, 0, size, bo->base.va, 0, AMDGPU_VM_PAGE_PRT, AMDGPU_VA_OP_MAP, 0, NULL);
       if (r) {
          fprintf(stderr, "radv/amdgpu: Failed to reserve a PRT VA region (%d).\n", r);
          result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
@@ -532,7 +563,7 @@ radv_amdgpu_winsys_bo_create(struct radeon_winsys *_ws, uint64_t size, unsigned
    r = ac_drm_bo_export(ws->dev, buf_handle, amdgpu_bo_handle_type_kms, &kms_handle);
    assert(!r);
 
-   r = radv_amdgpu_bo_va_op(ws, kms_handle, 0, size, va, flags, 0, AMDGPU_VA_OP_MAP);
+   r = radv_amdgpu_bo_va_op(ws, kms_handle, 0, size, va, flags, 0, AMDGPU_VA_OP_MAP, 0, NULL);
    if (r) {
       result = VK_ERROR_UNKNOWN;
       goto error_va_map;
@@ -808,7 +839,7 @@ radv_amdgpu_winsys_bo_from_fd(struct radeon_winsys *_ws, int fd, unsigned priori
       goto error_query;
    }
 
-   r = radv_amdgpu_bo_va_op(ws, kms_handle, 0, result.alloc_size, va, 0, 0, AMDGPU_VA_OP_MAP);
+   r = radv_amdgpu_bo_va_op(ws, kms_handle, 0, result.alloc_size, va, 0, 0, AMDGPU_VA_OP_MAP, 0, NULL);
    if (r) {
       vk_result = VK_ERROR_UNKNOWN;
       goto error_va_map;