1. 24 Feb, 2022 27 commits
    • Thomas Andersen's avatar
      58f956c8
    • Thomas Andersen's avatar
      vulkan: avoid warning about unused function · ca6e4126
      Thomas Andersen authored
      VK_DEFINE_NONDISP_HANDLE_CASTS defines two functions.
      In some cases only one or the other is used. Marking
      them both unused here to avoid warnings.
      
      Fixes a clang warning about unused static inlined functions.
      ca6e4126
    • Thomas Andersen's avatar
      panfrost: avoid warning about unused function · 30bdd6e7
      Thomas Andersen authored
      This function is only used if PAN_ARCH >= 5
      
      Fixes a clang warning about unused static inlined functions.
      30bdd6e7
    • Thomas Andersen's avatar
      llvmpipe: drop unused function · b253e841
      Thomas Andersen authored
      Fixes a clang warning about unused static inlined functions.
      b253e841
    • Thomas Andersen's avatar
      llvmpipe: mark function unused · aa2c9d24
      Thomas Andersen authored
      build_masks is only used if neither PIPE_ARCH_SSE or
      _ARCH_PWR8 && UTIL_ARCH_LITTLE_ENDIAN.
      Adding a #if around build_masks feels a bit fragile so
      I opted for just marking it unused.
      
      Fixes a clang warning about unused static inlined functions.
      aa2c9d24
    • Thomas Andersen's avatar
      spirv: mark function unused · 2f52fd48
      Thomas Andersen authored
      It is unused, but seems relevant to keep around.
      
      Fixes a clang warning about unused static inlined functions.
      2f52fd48
    • Mike Blumenkrantz's avatar
      zink: add a flake channel · b124f83b
      Mike Blumenkrantz authored and Marge Bot's avatar Marge Bot committed
      
      Reviewed-by: Emma Anholt's avatarEmma Anholt <emma@anholt.net>
      Part-of: <mesa/mesa!15129>
      b124f83b
    • Alyssa Rosenzweig's avatar
      pan/bi: Unit test message preloading optimization · cd2a4cc4
      Alyssa Rosenzweig authored
      
      
      To make sure it is applied in the cases we expect it to be, to avoid code
      generation regressions. Functional regressions are expected to be caught by
      integration-testing, so that is not focused on here.
      Signed-off-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa@collabora.com>
      Part-of: <mesa/mesa!9438>
      cd2a4cc4
    • Alyssa Rosenzweig's avatar
      pan/bi: Support message preloading · eb1479bd
      Alyssa Rosenzweig authored
      
      
      Preload LD_VAR_IMM or VAR_TEX instructions in the first block of fragment
      shaders on v7. Preloaded messages write to fixed registers; when replacing
      instructions we insert moves from the registers at the start of the program and
      hope coalescing goes to town. (Admittedly we don't do any coalescing yet...)
      The extra moves hurts instruction count in some cases; the win for cycle count
      should cancel this out. When we get smarter copy prop or RA, those moves should
      go away anyway.
      
      This optimization may hurt register pressure by extending the lifetime of up to
      eight registers written in the first block. This is expected to be acceptable:
      on a large shader-db, there are no additional spills/fills, and only two shaders
      are hurt on thread count.
      
      This optimization only applies to v7, as the hardware was not introduced on v6
      and was removed for Valhall.
      
      total instructions in shared programs: 2451624 -> 2454286 (0.11%)
      instructions in affected programs: 909046 -> 911708 (0.29%)
      helped: 4719
      HURT: 3341
      helped stats (abs) min: 1.0 max: 10.0 x̄: 1.49 x̃: 1
      helped stats (rel) min: 0.08% max: 33.33% x̄: 6.79% x̃: 3.92%
      HURT stats (abs)   min: 1.0 max: 50.0 x̄: 2.90 x̃: 2
      HURT stats (rel)   min: 0.12% max: 66.67% x̄: 6.39% x̃: 3.45%
      95% mean confidence interval for instructions value: 0.27 0.39
      95% mean confidence interval for instructions %-change: -1.55% -1.11%
      Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).
      
      total tuples in shared programs: 1969529 -> 1963429 (-0.31%)
      tuples in affected programs: 601327 -> 595227 (-1.01%)
      helped: 5907
      HURT: 1297
      helped stats (abs) min: 1.0 max: 8.0 x̄: 1.41 x̃: 1
      helped stats (rel) min: 0.07% max: 33.33% x̄: 7.25% x̃: 5.26%
      HURT stats (abs)   min: 1.0 max: 40.0 x̄: 1.73 x̃: 1
      HURT stats (rel)   min: 0.16% max: 31.75% x̄: 3.38% x̃: 2.02%
      95% mean confidence interval for tuples value: -0.88 -0.81
      95% mean confidence interval for tuples %-change: -5.52% -5.15%
      Tuples are helped.
      
      total clauses in shared programs: 401689 -> 387830 (-3.45%)
      clauses in affected programs: 136944 -> 123085 (-10.12%)
      helped: 8427
      HURT: 4
      helped stats (abs) min: 1.0 max: 4.0 x̄: 1.65 x̃: 2
      helped stats (rel) min: 0.49% max: 50.00% x̄: 19.88% x̃: 18.18%
      HURT stats (abs)   min: 1.0 max: 4.0 x̄: 2.50 x̃: 2
      HURT stats (rel)   min: 1.96% max: 19.05% x̄: 14.18% x̃: 17.86%
      95% mean confidence interval for clauses value: -1.66 -1.63
      95% mean confidence interval for clauses %-change: -20.15% -19.58%
      Clauses are helped.
      
      total cycles in shared programs: 202735.83 -> 201862.21 (-0.43%)
      cycles in affected programs: 16295.46 -> 15421.83 (-5.36%)
      helped: 3349
      HURT: 1962
      helped stats (abs) min: 0.041665999999999315 max: 1.0 x̄: 0.32 x̃: 0
      helped stats (rel) min: 0.24% max: 100.00% x̄: 40.77% x̃: 33.33%
      HURT stats (abs)   min: 0.041665999999999315 max: 1.5833329999999997 x̄: 0.10 x̃: 0
      HURT stats (rel)   min: 0.09% max: 31.40% x̄: 2.95% x̃: 1.94%
      95% mean confidence interval for cycles value: -0.17 -0.16
      95% mean confidence interval for cycles %-change: -25.48% -23.76%
      Cycles are helped.
      
      total arith in shared programs: 74665.50 -> 74920.00 (0.34%)
      arith in affected programs: 16059.92 -> 16314.42 (1.58%)
      helped: 860
      HURT: 3409
      helped stats (abs) min: 0.041665999999999315 max: 0.25 x̄: 0.06 x̃: 0
      helped stats (rel) min: 0.24% max: 37.50% x̄: 4.73% x̃: 2.56%
      HURT stats (abs)   min: 0.041665999999999315 max: 1.5833329999999997 x̄: 0.09 x̃: 0
      HURT stats (rel)   min: 0.09% max: 100.00% x̄: 8.99% x̃: 4.21%
      95% mean confidence interval for arith value: 0.06 0.06
      95% mean confidence interval for arith %-change: 5.83% 6.62%
      Arith are HURT.
      
      total texture in shared programs: 13083.50 -> 11877 (-9.22%)
      texture in affected programs: 1663 -> 456.50 (-72.55%)
      helped: 2377
      HURT: 3
      helped stats (abs) min: 0.5 max: 1.0 x̄: 0.51 x̃: 0
      helped stats (rel) min: 6.25% max: 100.00% x̄: 87.12% x̃: 100.00%
      HURT stats (abs)   min: 0.5 max: 0.5 x̄: 0.50 x̃: 0
      HURT stats (rel)   min: 0.00% max: 25.00% x̄: 16.67% x̃: 25.00%
      95% mean confidence interval for texture value: -0.51 -0.50
      95% mean confidence interval for texture %-change: -87.98% -86.00%
      Texture are helped.
      
      total vary in shared programs: 10220.62 -> 4183.88 (-59.06%)
      vary in affected programs: 10126.50 -> 4089.75 (-59.61%)
      helped: 8538
      HURT: 0
      helped stats (abs) min: 0.125 max: 1.0 x̄: 0.71 x̃: 0
      helped stats (rel) min: 7.14% max: 100.00% x̄: 74.74% x̃: 87.50%
      95% mean confidence interval for vary value: -0.71 -0.70
      95% mean confidence interval for vary %-change: -75.32% -74.16%
      Vary are helped.
      
      total quadwords in shared programs: 1766717 -> 1757161 (-0.54%)
      quadwords in affected programs: 553801 -> 544245 (-1.73%)
      helped: 6760
      HURT: 711
      helped stats (abs) min: 1.0 max: 11.0 x̄: 1.58 x̃: 1
      helped stats (rel) min: 0.09% max: 29.41% x̄: 5.31% x̃: 4.84%
      HURT stats (abs)   min: 1.0 max: 33.0 x̄: 1.54 x̃: 1
      HURT stats (rel)   min: 0.10% max: 31.13% x̄: 2.53% x̃: 1.61%
      95% mean confidence interval for quadwords value: -1.31 -1.25
      95% mean confidence interval for quadwords %-change: -4.67% -4.46%
      Quadwords are helped.
      
      total threads in shared programs: 52899 -> 52897 (<.01%)
      threads in affected programs: 4 -> 2 (-50.00%)
      helped: 0
      HURT: 2
      
      total preloads in shared programs: 0 -> 116492
      preloads in affected programs: 0 -> 116492
      helped: 0
      HURT: 8604
      HURT stats (abs)   min: 2.0 max: 24.0 x̄: 13.54 x̃: 14
      HURT stats (rel)   min: 0.00% max: 0.00% x̄: 0.00% x̃: 0.00%
      95% mean confidence interval for preloads value: 13.45 13.63
      95% mean confidence interval for preloads %-change: 0.00% 0.00%
      Preloads are HURT.
      Signed-off-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa@collabora.com>
      Part-of: <mesa/mesa!9438>
      eb1479bd
    • Alyssa Rosenzweig's avatar
      pan/bi: Account for message preloading in shaderdb · c8437cd4
      Alyssa Rosenzweig authored
      
      
      If a message-passing instruction like LD_VAR is preloaded, it will no longer be
      counted in the shader cycle counts. Add a special message preload counter that
      approximates the cost of preloading, so this information doesn't get a lost.
      Signed-off-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa@collabora.com>
      Part-of: <mesa/mesa!9438>
      c8437cd4
    • Alyssa Rosenzweig's avatar
      pan/bi: Add bi_before_nonempty_block helper · 19541dc8
      Alyssa Rosenzweig authored
      
      
      To be used in the message preloading pass.
      Signed-off-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa@collabora.com>
      Part-of: <mesa/mesa!9438>
      19541dc8
    • Alyssa Rosenzweig's avatar
      panfrost: Pack message preloads from compiler · 6618697e
      Alyssa Rosenzweig authored
      
      
      Include full message preload descriptors in the RSD on v7, and do the obvious
      packing for fragment shader message preloads.
      Signed-off-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa@collabora.com>
      Part-of: <mesa/mesa!9438>
      6618697e
    • Alyssa Rosenzweig's avatar
      panfrost: Add an unpacked message preload struct · bd06a266
      Alyssa Rosenzweig authored
      
      
      The compiler will soon produce preloaded messages, but it should not pack them
      itself, as this would require depending on GenXML or handcoding bitfields / bit
      packs in the compiler. Instead, add a struct encoding the unpacked form of the
      message, used as ABI between the compiler and the common driver.
      Signed-off-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa@collabora.com>
      Part-of: <mesa/mesa!9438>
      bd06a266
    • Alyssa Rosenzweig's avatar
      panfrost: Remove Message Preload Descriptor from v6.xml · 2d0c4973
      Alyssa Rosenzweig authored
      
      
      It is an anachronism, as this descriptor was added in v7 and, seemingly, removed
      immediately after. Good work.
      Signed-off-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa@collabora.com>
      Part-of: <mesa/mesa!9438>
      2d0c4973
    • Igor Torrente's avatar
      venus: add macros to help with future extensions · b130f8f4
      Igor Torrente authored and Marge Bot's avatar Marge Bot committed
      
      
      Currently we have to add almost the same code to the
      `vn_physical_device_init_{features, properties}` to add
      the extension to the `physical_dev->{features, properties}`
      list.
      
      These macros improves the code reusage.
      Signed-off-by: Igor Torrente's avatarIgor Torrente <igor.torrente@collabora.com>
      Part-of: <mesa/mesa!15059>
      b130f8f4
    • Alyssa Rosenzweig's avatar
      panfrost/ci: Move T860 flake to skip · 43bbe367
      Alyssa Rosenzweig authored and Marge Bot's avatar Marge Bot committed
      
      
      Actually an xfail but occassionally passes and gives us no new information, only
      noise.
      Signed-off-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa@collabora.com>
      Suggested-and-acked-by: Daniel Stone's avatarDaniel Stone <daniels@collabora.com>
      Part-of: <mesa/mesa!15154>
      43bbe367
    • Alyssa Rosenzweig's avatar
      panfrost/ci: Move T720 flakes to skips · 5c07f7c4
      Alyssa Rosenzweig authored and Marge Bot's avatar Marge Bot committed
      
      
      Doesn't seem like these will be resolved anytime soon..
      Signed-off-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa@collabora.com>
      Suggested-and-acked-by: Daniel Stone's avatarDaniel Stone <daniels@collabora.com>
      Part-of: <mesa/mesa!15154>
      5c07f7c4
    • Tomeu Vizoso's avatar
      Revert "ci: Disable jobs to the Collabora lab" · eecc62cc
      Tomeu Vizoso authored
      This reverts commit f692bda4.
      
      Part-of: <mesa/mesa!15153>
      eecc62cc
    • Iago Toral's avatar
      broadcom/compiler: move uniforms right before their first use after scheduling · cf99584f
      Iago Toral authored and Marge Bot's avatar Marge Bot committed
      
      
      On V3D the quality of the code we generate is significantly affected by
      how we decide to assign accumulators during register allocation, which
      is determined by liveness, favoring short-lived temps.
      
      There are many shaders that end up doing a whole lot of uniform loads
      first, and using them later, which is very inconvenient for our register
      allocation process because this increases uniform liveness and causes
      us to use accumulators less efficientely, leading to significant churn.
      
      To fix this, we move uniforms right before their first use in the same
      block, but we need to do this after NIR scheduling, which means we are
      doing it in non-SSA form, since the scheduler has a tendency to undo
      this optimization and it is not easy to modify it to avoid it, since it
      works in more abstract terms, using instruction dependencies, estimated
      register pressure and instruction delay information to do its work,
      which are very different concepts.
      
      total instructions in shared programs: 13316738 -> 13033613 (-2.13%)
      instructions in affected programs: 10389172 -> 10106047 (-2.73%)
      helped: 55442
      HURT: 16144
      
      total threads in shared programs: 413722 -> 415048 (0.32%)
      threads in affected programs: 1428 -> 2754 (92.86%)
      helped: 680
      HURT: 17
      
      total loops in shared programs: 1716 -> 1690 (-1.52%)
      loops in affected programs: 26 -> 0
      helped: 26
      HURT: 0
      
      total uniforms in shared programs: 3704313 -> 3705181 (0.02%)
      uniforms in affected programs: 687730 -> 688598 (0.13%)
      helped: 2920
      HURT: 7384
      
      total max-temps in shared programs: 2364785 -> 2175190 (-8.02%)
      max-temps in affected programs: 1215387 -> 1025792 (-15.60%)
      helped: 49667
      HURT: 1556
      
      total spills in shared programs: 4241 -> 4248 (0.17%)
      spills in affected programs: 642 -> 649 (1.09%)
      helped: 11
      HURT: 19
      
      total fills in shared programs: 6115 -> 6125 (0.16%)
      fills in affected programs: 1276 -> 1286 (0.78%)
      helped: 11
      HURT: 21
      
      total sfu-stalls in shared programs: 34381 -> 36578 (6.39%)
      sfu-stalls in affected programs: 16055 -> 18252 (13.68%)
      helped: 3647
      HURT: 5206
      Reviewed-by: Alejandro Piñeiro's avatarAlejandro Piñeiro <apinheiro@igalia.com>
      Part-of: <mesa/mesa!15056>
      cf99584f
    • Iago Toral's avatar
      nir/nir_opt_move: handle non-SSA defs · f1d20ec6
      Iago Toral authored and Marge Bot's avatar Marge Bot committed
      
      
      We just skip register defs and avoid moving register reads across them.
      This allows us to run this pass in non-SSA form.
      Reviewed-by: Daniel Schürmann's avatarDaniel Schürmann <daniel@schuermann.dev>
      Part-of: <mesa/mesa!15056>
      f1d20ec6
    • Iago Toral's avatar
      nir: add a nir_instr_def_is_register helper · fe2249ea
      Iago Toral authored and Marge Bot's avatar Marge Bot committed
      
      
      This returns true if the instruction has a dest that is not an SSA value.
      Reviewed-by: Daniel Schürmann's avatarDaniel Schürmann <daniel@schuermann.dev>
      Part-of: <mesa/mesa!15056>
      fe2249ea
    • Iago Toral's avatar
      nir/nir_opt_move: allow to move uniform loads · 0a044687
      Iago Toral authored and Marge Bot's avatar Marge Bot committed
      
      Reviewed-by: Jason Ekstrand's avatarJason Ekstrand <jason.ekstrand@collabora.com>
      Part-of: <mesa/mesa!15056>
      0a044687
    • Tomeu Vizoso's avatar
      ci: Disable jobs to the Collabora lab · f692bda4
      Tomeu Vizoso authored
      
      
      In anticipation of infrastructure work.
      
      This commit is to be reverted later in the day.
      Signed-off-by: Tomeu Vizoso's avatarTomeu Vizoso <tomeu.vizoso@collabora.com>
      Part-of: <mesa/mesa!15150>
      f692bda4
    • Tomeu Vizoso's avatar
      ci: Allow disabling the whole of the Collabora farm · c0695bb4
      Tomeu Vizoso authored
      
      
      Add a global-level variable that allows disabling all jobs that would
      have gone to the Collabora lab, to be used in case of outages.
      Signed-off-by: Tomeu Vizoso's avatarTomeu Vizoso <tomeu.vizoso@collabora.com>
      Part-of: <mesa/mesa!15150>
      c0695bb4
    • Emma Anholt's avatar
      ci/lvp: Update the asan fails list. · a5fa7e04
      Emma Anholt authored and Marge Bot's avatar Marge Bot committed
      
      
      Many tests had been fixed but weren't being run due to test reshuffles
      from uprevs.  Add some explanations for what remains.
      Acked-by: Mike Blumenkrantz's avatarMike Blumenkrantz <michael.blumenkrantz@gmail.com>
      Part-of: <mesa/mesa!15133>
      a5fa7e04
    • Alyssa Rosenzweig's avatar
      pan/bi: Reorder pushed uniforms to avoid moves · 6b2eda6b
      Alyssa Rosenzweig authored and Marge Bot's avatar Marge Bot committed
      
      
      On Bifrost and Valhall, push uniforms are loaded into Fast Access Uniform
      Random Access Memory (FAU-RAM). FAU-RAM is organized as an array of 64-bit
      slots. A given tuple (Bifrost) or instruction (Valhall) may access at most a
      single 64-bit slot. If an instruction requires uniforms from multiple 64-bit
      slots, a uniform-to-register move must be inserted to avoid the hazard. However,
      if an instruction requires a pair of 32-bit uniforms from the same 64-bit slot,
      no move is required.
      
      To reduce the number of moves we emit, this commit adds an optimization pass
      that reorders pushed uniforms, trying to group uniforms used by the same
      instruction. The pass works by creating a graph of pushed uniforms, where edges
      denote the "both 32-bit uniforms required by the same instruction" relationship.
      We perform depth-first search on this graph to find the connected components,
      where each connected component is a cluster of uniforms that are used together.
      We then select pairs of uniforms from each connected component. The remaining
      unpaired uniforms (from components of odd sizes) are paired together
      arbitrarily.
      
      In principle, we should weight the graph by number of occurences and choose
      pairs that maximize the total selected edge weight. This is left for
      future work, as it is nontrivial -- selecting these edges optimally appears to
      be NP-hard at first blush.
      
      Implementation note: As position and varying shaders share FAU on Bifrost, extra
      care is taken with a `push_offset` shader stage info parameter that ensures
      varying shaders do not reorder uniforms selected by the previous position
      shader.
      
      total instructions in shared programs: 2503343 -> 2451758 (-2.06%)
      instructions in affected programs: 1553309 -> 1501724 (-3.32%)
      helped: 14256
      HURT: 8
      helped stats (abs) min: 1.0 max: 80.0 x̄: 3.62 x̃: 3
      helped stats (rel) min: 0.06% max: 36.36% x̄: 7.31% x̃: 6.67%
      HURT stats (abs)   min: 1.0 max: 2.0 x̄: 1.38 x̃: 1
      HURT stats (rel)   min: 1.30% max: 12.50% x̄: 4.99% x̃: 3.85%
      95% mean confidence interval for instructions value: -3.66 -3.58
      95% mean confidence interval for instructions %-change: -7.41% -7.20%
      Instructions are helped.
      
      total tuples in shared programs: 2008399 -> 1969627 (-1.93%)
      tuples in affected programs: 1146344 -> 1107572 (-3.38%)
      helped: 12867
      HURT: 147
      helped stats (abs) min: 1.0 max: 61.0 x̄: 3.03 x̃: 2
      helped stats (rel) min: 0.17% max: 42.86% x̄: 6.79% x̃: 4.65%
      HURT stats (abs)   min: 1.0 max: 3.0 x̄: 1.20 x̃: 1
      HURT stats (rel)   min: 0.29% max: 20.00% x̄: 2.12% x̃: 1.19%
      95% mean confidence interval for tuples value: -3.03 -2.93
      95% mean confidence interval for tuples %-change: -6.82% -6.57%
      Tuples are helped.
      
      total clauses in shared programs: 408005 -> 401708 (-1.54%)
      clauses in affected programs: 90760 -> 84463 (-6.94%)
      helped: 6006
      HURT: 164
      helped stats (abs) min: 1.0 max: 9.0 x̄: 1.08 x̃: 1
      helped stats (rel) min: 0.45% max: 33.33% x̄: 12.44% x̃: 14.29%
      HURT stats (abs)   min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
      HURT stats (rel)   min: 1.64% max: 25.00% x̄: 9.81% x̃: 5.26%
      95% mean confidence interval for clauses value: -1.03 -1.01
      95% mean confidence interval for clauses %-change: -12.03% -11.66%
      Clauses are helped.
      
      total cycles in shared programs: 203308.37 -> 202737.83 (-0.28%)
      cycles in affected programs: 19264.71 -> 18694.17 (-2.96%)
      helped: 3024
      HURT: 41
      helped stats (abs) min: 0.041665999999999315 max: 2.5416680000000014 x̄: 0.19 x̃: 0
      helped stats (rel) min: 0.17% max: 33.33% x̄: 3.83% x̃: 2.83%
      HURT stats (abs)   min: 0.041665999999999315 max: 0.125 x̄: 0.06 x̃: 0
      HURT stats (rel)   min: 0.30% max: 5.88% x̄: 1.41% x̃: 0.93%
      95% mean confidence interval for cycles value: -0.19 -0.18
      95% mean confidence interval for cycles %-change: -3.89% -3.64%
      Cycles are helped.
      
      total arith in shared programs: 76265.67 -> 74669.25 (-2.09%)
      arith in affected programs: 45001.50 -> 43405.08 (-3.55%)
      helped: 12945
      HURT: 97
      helped stats (abs) min: 0.041665999999999315 max: 2.5416680000000014 x̄: 0.12 x̃: 0
      helped stats (rel) min: 0.17% max: 50.00% x̄: 8.06% x̃: 4.88%
      HURT stats (abs)   min: 0.041665999999999315 max: 0.125 x̄: 0.05 x̃: 0
      HURT stats (rel)   min: 0.21% max: 33.33% x̄: 2.16% x̃: 0.96%
      95% mean confidence interval for arith value: -0.12 -0.12
      95% mean confidence interval for arith %-change: -8.16% -7.81%
      Arith are helped.
      
      total quadwords in shared programs: 1796563 -> 1766803 (-1.66%)
      quadwords in affected programs: 948830 -> 919070 (-3.14%)
      helped: 12078
      HURT: 219
      helped stats (abs) min: 1.0 max: 42.0 x̄: 2.49 x̃: 2
      helped stats (rel) min: 0.10% max: 33.33% x̄: 5.57% x̃: 5.26%
      HURT stats (abs)   min: 1.0 max: 4.0 x̄: 1.21 x̃: 1
      HURT stats (rel)   min: 0.33% max: 6.67% x̄: 2.00% x̃: 1.14%
      95% mean confidence interval for quadwords value: -2.46 -2.38
      95% mean confidence interval for quadwords %-change: -5.52% -5.36%
      Quadwords are helped.
      Signed-off-by: Alyssa Rosenzweig's avatarAlyssa Rosenzweig <alyssa@collabora.com>
      Part-of: <mesa/mesa!14163>
      6b2eda6b
    • Timothy Arceri's avatar
      glsl/nir: free GLSL IR right after we convert to NIR · 6eec8fcb
      Timothy Arceri authored and Marge Bot's avatar Marge Bot committed
      
      
      Gives us memory back faster which is useful for pathalogical CTS
      tests.
      
      The GLSL IR was previously used after converting to NIR for things
      like building the GL resource list but we have had a NIR version
      for this for some time and I don't believe there are any other
      use cases left for keeping the old IR hanging around this long.
      Reviewed-by: Emma Anholt's avatarEmma Anholt <emma@anholt.net>
      Part-of: <mesa/mesa!15127>
      6eec8fcb
  2. 23 Feb, 2022 13 commits