- 04 Jul, 2021 2 commits
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Thomas Andersen authored
ifind_msb_rev was introduced in a5747f8a . ifind_msb_rev guards against src0 being both 0 or -1 at the same time. That is always true. This patch changes it to check for those values individually. Spotted from a compile warning. Reviewed-by:
Ian Romanick <ian.d.romanick@intel.com> Fixes: a5747f8a (\"nir: add opcodes for *find_msb_rev and lowering\") Part-of: <mesa/mesa!11630>
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+ 9.31% drawover:gdrv0 iris_dri.so [.] iris_binder_reserve_3d + 2.36% drawover:gdrv0 iris_dri.so [.] iris_binder_reserve_3d If the app never uses compute, then the compute bindings bit will always be dirty causing these two paths never get shortcuts. Reviewed-by:
Kenneth Graunke <kenneth@whitecape.org>
Part-of: <mesa/mesa!11699>
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- 03 Jul, 2021 6 commits
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Icecream95 authored
If all of the used values from a UBO are pushed, it doesn't need to be uploaded. Part-of: <mesa/mesa!11700>
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Icecream95 authored
Part-of: <mesa/mesa!11700>
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Icecream95 authored
Part-of: <mesa/mesa!11700>
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Icecream95 authored
It is unused. Part-of: <mesa/mesa!11700>
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Zoltán Böszörményi authored
Add PCI IDs based in pci_ids/i965_pci_ids.h and move crocus before iris in driver_map[]. This allows Xorg to load the crocus driver since iris would claim the devices handled by crocus (because the i915 kernel driver is used for all Intel devices) then fail during initialization. Signed-off-by:
Zoltán Böszörményi <zboszor@gmail.com> Reviewed-by:
Dave Airlie <airlied@redhat.com> Part-of: <mesa/mesa!11694>
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Zoltán Böszörményi authored
Signed-off-by:
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- 02 Jul, 2021 32 commits
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Kenneth Graunke authoredThe intention here was to pass VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT to select_memory_types() when requesting device local memory, or simply pass 0 for the prime blit destination which should be in system memory. Unfortunately, that meant we did (type.propertyFlags & 0) == 0 which was vacuously true, causing us to not filter out device local types. Fixes hybrid display of Vulkan apps on Intel TGL+DG1 systems. Tested-by:
Luis Felipe Strano Moraes <luis.strano@intel.com> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: 
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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Emma Anholt authored
Even with the wrap mode forced to REPEAT, we get undefined results in CelShading when the Y channel is unwritten since the beginning of the program. I dropped the coords==0 case in the process, since that's not possible and made the 1D case confusing. Part-of: <mesa/mesa!11457>
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Emma Anholt authored
There are no 1D textures in HW, so we use 2D, but at the shader level there no Y coordinate to 1D sampling, so we need that value to be ignored. WRAP mode can get us that. Part-of: <mesa/mesa!11457>
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Adam Jackson authored
As written this would require that the driver be built before we looked at the option. This is wrong because it affects code outside of the driver, it's in libGL's PCI ID table. This is sort of harmless for crocus at the moment, but for iris you would need to build it in order to remove it from the table; if you built just i965 and tried to run it against gen9, the libGL you just built would direct the loader to the iris driver you just didn't, and setup would fail, which is: goofy. Reviewed-by:
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Kenneth Graunke authored
This was used in the heuristics for deciding whether to CPU map, but those have since been deleted, so this is now unused. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <mesa/mesa!11644> -
Kenneth Graunke authored
If the caller has asked for a coherent BO with snooping, and the kernel fails to set it for whatever reason, we were happily returning them a non-coherent buffer. This isn't what they wanted and could lead to surprising results. Better to simply fail the allocation. Probably. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <mesa/mesa!11644> -
Kenneth Graunke authored
On integrated GPUs without LLC, we enable snooping when someone requests coherency for a buffer. (With LLC, it's already coherent.) For discrete GPUs...if someone requests coherency, we allocate the buffer in SMEM and resort to WC maps rather than WB maps with CPU caches enabled. There's no snooping to enable, and calling this ioctl is nonsensical, and may fail. Reviewed-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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Emma Anholt authored
Part-of: <mesa/mesa!11668>
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Emma Anholt authored
Closes: #4973 Part-of: <mesa/mesa!11668>
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Samuel Pitoiset authored
With HTILE only, all values between 0.0 and 1.0 are fetchable. This should allow more fast clears for depth surfaces where TC-compat HTILE is disabled. Signed-off-by:
Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by:
Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <mesa/mesa!10035>
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Samuel Pitoiset authored
VK_EXT_depth_range_unrestricted removes the restriction that the clear value must be between 0.0 and 1.0. Signed-off-by:
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Samuel Pitoiset authored
The HTILE clear code is now computed based on the floating point value. Signed-off-by:
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Samuel Pitoiset authored
Signed-off-by:
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Samuel Pitoiset authored
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Michel Dänzer authored
Fixes: d6287a94 "gallium: rename 'state tracker' to 'frontend'" Reviewed-by:
Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <mesa/mesa!11676> -
Jesse Natalie authored
For images, variable data includes the format. For samplers, variable data is used for OpenCL inline samplers. When converting a variable from one to the other, zero out the data so we don't accidentally interpret a converted image as an inline sampler. Fixes: fa677c86 ("nir_lower_readonly_images_to_tex: Support non-CL semantics") Acked-by:
Enrico Galli <enrico.galli@intel.com> Reviewed-by:
Jason Ekstrand <jason@jlekstrand.net>
Part-of: <mesa/mesa!11674> -
Mike Blumenkrantz authoredReviewed-by:
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Mike Blumenkrantz authored
this is super hacky for the non-timeline case but whatever Reviewed-by:
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Mike Blumenkrantz authored
stop using the memory bind offset Reviewed-by:
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Mike Blumenkrantz authored
zink_resource_object::offset is the memory offset, which is unrelated to the offset in a buffer Reviewed-by:
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Mike Blumenkrantz authored
zink_resource_object::size is the size of the memory allocation, which is effectively unrelated Reviewed-by:
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Mike Blumenkrantz authored
this doesn't apply to any image/buffer operations, it's solely for memory allocation/binding/mapping Reviewed-by:
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Mike Blumenkrantz authored
coherent is already synchronized Reviewed-by:
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Mike Blumenkrantz authored
consistency++ Reviewed-by:
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Daniel Stone authoredWhen we exit early having failed to find any candidate cache files to evict, don't leak the list head whilst doing so. Signed-off-by:
Daniel Stone <daniels@collabora.com>
Fixes: f58e6fee ("util/disk_cache: delete more cache items in one go when full")
Ref: <mesa/mesa!11523
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Reviewed-By: 
Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> Part-of: <mesa/mesa!11682>
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Mike Blumenkrantz authored
redundant at this point; no functional changes Reviewed-by:
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Mike Blumenkrantz authored
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Mike Blumenkrantz authored
batch tracking has until now been the same as refcounting, but this is inefficient and incurs additional overhead from constant atomic ops, so make them separate Reviewed-by:
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Mike Blumenkrantz authored
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Mike Blumenkrantz authored
I think maybe I misunderstood how things worked, or there were issues generally with resource lifetimes, or whatever, but this isn't needed anymore Reviewed-by:
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Mike Blumenkrantz authored
this will be handled automatically Reviewed-by:
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Mike Blumenkrantz authored
this makes c++ happy Reviewed-by:
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