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Commits (22)
  • Lyude Paul's avatar
    wip bf assembler · 6e8a1f2f
    Lyude Paul authored
    6e8a1f2f
  • Lyude Paul's avatar
    more wip · 4b85db43
    Lyude Paul authored
    4b85db43
  • Lyude Paul's avatar
    more wip · 7a7d2c2c
    Lyude Paul authored
    7a7d2c2c
  • Lyude Paul's avatar
    more wip · 5816c901
    Lyude Paul authored
    5816c901
  • Lyude Paul's avatar
    more wip · 489a41e3
    Lyude Paul authored
    489a41e3
  • Lyude Paul's avatar
    wip: finished port assignment for register/uniform reads · 838b121f
    Lyude Paul authored
    Constants will be handled later after we've got encoding the rest of the
    instruction down. For now we'll rely on samples that only use the 0
    constant in addition to other special sources, uniforms, and registers
    as we don't need full constant support to encode 0.
    838b121f
  • Lyude Paul's avatar
    wip: add Clause objects, rework and implement base for op parsing, +more · 0e73cf94
    Lyude Paul authored
    Add a lot more output in __repr()__
    
    TODO:
     - Start encoding register files
     - Fix data_reg extaction with ADD operation parsing
    0e73cf94
  • Lyude Paul's avatar
    wip: Finish (HOPEFULLY?) register read/write port assignment · 9b8c2dcc
    Lyude Paul authored
    I have some slight concerns about this which I'm not sure are valid or
    not. if we're reading and writing from a port that's using port 3, does
    the previous instruction (which the writes for said port would be for)
    need to be using port 3 as the source??
    chris if you see this i'm confused
    
    anyway, IF THAT ISN'T THE CASE then this should be correct. this took
    absolutely forever.
    
    also nice verbosity things got added
    9b8c2dcc
  • Lyude Paul's avatar
    9b761dfb
  • Lyude Paul's avatar
    wip: Almost working constant support · 10d2ddb9
    Lyude Paul authored
    This part is a bit difficult, as I think the compiler is doing something
    slightly different here then I expected. Before I begin, the term
    "Immediate slot" here refers to a single 64 bit immediate. I've taken to
    calling it a slot as the compiler may or may not use it for storing 2
    32bit immediates, or a single 64 bit immediate, while additionally
    attempting to reuse immediate slots whenever possible.
    
    Mainly: it looks like that when the compiler starts assigning immediates
    to immediate slots, if an instruction's stages only end up using half of
    a single immediate slot, it keeps the immediate slot as "pending" and
    doesn't actually attempt to assign it to a constant index until the
    entire clause has finished, where it may reuse the slot if there's
    another instruction later in the clause that uses one of the immediates
    in the pending immediate slot, along with an additional immediate. I had
    assumed this would have been done the opposite way: where we would
    assign an immediate slot an index immediately (regardless of whether or
    not it has more space for immediates), then potentially add another
    immediate into the slot for a later instruction in order to reuse it.
    Basically: it's just that the compiler is assigning immediate slots in
    reverse to the order we expected.
    10d2ddb9
  • Lyude Paul's avatar
    wip: Get constant assignments fully working · 78332e98
    Lyude Paul authored
    This seems to match up with the compiler's output, hooray!
    78332e98
  • Lyude Paul's avatar
    wip: Don't forget to resolve half-full slots · f98fd720
    Lyude Paul authored
    But, we're stil not matching up with some of the other samples I have...
    f98fd720
  • Lyude Paul's avatar
    wip: Add support for uniforms and fix opcode order · 3b3c7e6c
    Lyude Paul authored
    The constant mystery is still unsolved, but I'm going to solve that at a
    later point after I get some feedback and am sure that what I'm seeing
    isn't something to do with the quadword paking algorithm
    
    Additionally: I've fixed up the opcode order, which was reversed (but I
    never noticed it since most instructions in my samples didn't have more
    than one or two srcs)
    3b3c7e6c
  • Lyude Paul's avatar
    working wip???? try encoding register files now · 4b306387
    Lyude Paul authored
    This needs additional verification and a closer look.
    4b306387
  • Lyude Paul's avatar
    more wip: don't invert register file · 68dd22dd
    Lyude Paul authored
    68dd22dd
  • Lyude Paul's avatar
  • Lyude Paul's avatar
    wip: Add ATEST parsing · 5c6a8d60
    Lyude Paul authored
    Look at how much easier this is! yay
    5c6a8d60
  • Lyude Paul's avatar
    wip: fixes for register file I need to document · 9154d763
    Lyude Paul authored
    p3 == p2 if only writing to p2 and not reading from p3!
    9154d763
  • Lyude Paul's avatar
    wip: slight cleanup + correct instruction encoding for simple instructions · a4dac95e
    Lyude Paul authored
    This currently includes any N src instructions, along with ATEST and
    BLEND instructions. The only value that should be slightly off now is
    the constant port on clauses with a large number of immediates, due to a
    difference with how the compiler assigns constants to slots
    a4dac95e
  • Lyude Paul's avatar
    wip: Add clause header encoding · a435811e
    Lyude Paul authored
    a435811e
  • Lyude Paul's avatar
    wip: Add the start of full clause encoding · 28b33fa0
    Lyude Paul authored
    You read that right! This adds a (apparently incorrect? I'm not sure
    what I've gotten wrong on this quite yet, but there are a couple bits
    off on all of the results) partially complete clause encoder that
    handles accumulating quad words of instructions, along with packing the
    first constant into those quadwords. Next step is encoding the quad
    words that contain the rest of the constants
    28b33fa0
  • Lyude Paul's avatar
    wip: almost working full clause encoding · 46303864
    Lyude Paul authored
    46303864
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