1. 10 Jul, 2018 4 commits
  2. 08 Jul, 2018 3 commits
  3. 07 Jul, 2018 3 commits
  4. 05 Jul, 2018 1 commit
  5. 02 Jul, 2018 1 commit
    • Lyude Paul's avatar
      wip: Add the start of full clause encoding · 28b33fa0
      Lyude Paul authored
      You read that right! This adds a (apparently incorrect? I'm not sure
      what I've gotten wrong on this quite yet, but there are a couple bits
      off on all of the results) partially complete clause encoder that
      handles accumulating quad words of instructions, along with packing the
      first constant into those quadwords. Next step is encoding the quad
      words that contain the rest of the constants
      28b33fa0
  6. 16 Jun, 2018 1 commit
  7. 09 Jun, 2018 1 commit
  8. 04 Jun, 2018 1 commit
  9. 02 Jun, 2018 2 commits
  10. 29 May, 2018 2 commits
  11. 28 May, 2018 4 commits
    • Lyude Paul's avatar
      wip: Add support for uniforms and fix opcode order · 3b3c7e6c
      Lyude Paul authored
      The constant mystery is still unsolved, but I'm going to solve that at a
      later point after I get some feedback and am sure that what I'm seeing
      isn't something to do with the quadword paking algorithm
      
      Additionally: I've fixed up the opcode order, which was reversed (but I
      never noticed it since most instructions in my samples didn't have more
      than one or two srcs)
      3b3c7e6c
    • Lyude Paul's avatar
      wip: Don't forget to resolve half-full slots · f98fd720
      Lyude Paul authored
      But, we're stil not matching up with some of the other samples I have...
      f98fd720
    • Lyude Paul's avatar
      wip: Get constant assignments fully working · 78332e98
      Lyude Paul authored
      This seems to match up with the compiler's output, hooray!
      78332e98
    • Lyude Paul's avatar
      wip: Almost working constant support · 10d2ddb9
      Lyude Paul authored
      This part is a bit difficult, as I think the compiler is doing something
      slightly different here then I expected. Before I begin, the term
      "Immediate slot" here refers to a single 64 bit immediate. I've taken to
      calling it a slot as the compiler may or may not use it for storing 2
      32bit immediates, or a single 64 bit immediate, while additionally
      attempting to reuse immediate slots whenever possible.
      
      Mainly: it looks like that when the compiler starts assigning immediates
      to immediate slots, if an instruction's stages only end up using half of
      a single immediate slot, it keeps the immediate slot as "pending" and
      doesn't actually attempt to assign it to a constant index until the
      entire clause has finished, where it may reuse the slot if there's
      another instruction later in the clause that uses one of the immediates
      in the pending immediate slot, along with an additional immediate. I had
      assumed this would have been done the opposite way: where we would
      assign an immediate slot an index immediately (regardless of whether or
      not it has more space for immediates), then potentially add another
      immediate into the slot for a later instruction in order to reuse it.
      Basically: it's just that the compiler is assigning immediate slots in
      reverse to the order we expected.
      10d2ddb9
  12. 17 May, 2018 1 commit
  13. 13 May, 2018 2 commits
    • Lyude Paul's avatar
      wip: Finish (HOPEFULLY?) register read/write port assignment · 9b8c2dcc
      Lyude Paul authored
      I have some slight concerns about this which I'm not sure are valid or
      not. if we're reading and writing from a port that's using port 3, does
      the previous instruction (which the writes for said port would be for)
      need to be using port 3 as the source??
      chris if you see this i'm confused
      
      anyway, IF THAT ISN'T THE CASE then this should be correct. this took
      absolutely forever.
      
      also nice verbosity things got added
      9b8c2dcc
    • Lyude Paul's avatar
      wip: add Clause objects, rework and implement base for op parsing, +more · 0e73cf94
      Lyude Paul authored
      Add a lot more output in __repr()__
      
      TODO:
       - Start encoding register files
       - Fix data_reg extaction with ADD operation parsing
      0e73cf94
  14. 07 May, 2018 1 commit
    • Lyude Paul's avatar
      wip: finished port assignment for register/uniform reads · 838b121f
      Lyude Paul authored
      Constants will be handled later after we've got encoding the rest of the
      instruction down. For now we'll rely on samples that only use the 0
      constant in addition to other special sources, uniforms, and registers
      as we don't need full constant support to encode 0.
      838b121f
  15. 29 Apr, 2018 1 commit
  16. 28 Apr, 2018 2 commits
  17. 24 Apr, 2018 1 commit
  18. 23 Apr, 2018 1 commit
  19. 26 Mar, 2018 4 commits
  20. 25 Mar, 2018 4 commits