Commit f98fd720 authored by Lyude Paul's avatar Lyude Paul

wip: Don't forget to resolve half-full slots

But, we're stil not matching up with some of the other samples I have...
parent 78332e98
......@@ -694,6 +694,10 @@ class RegisterFile:
self.write_regs = dict()
self.__const_port = None
def __repr__(self):
return '<RegisterFile at 0x%x; ports=%s, const_port=%s>' % (
id(self), self.ports, self.const_port)
@property
def const_port(self):
return self.__const_port
......@@ -895,6 +899,9 @@ class Clause:
return self.__contents.__len__()
def add_immediate(self, token):
if token in self.__contents:
return
if self.bitlen + token.bitlen > 64:
raise ParsingException('Too many constants for one instruction cycle')
self.__contents.append(token)
......@@ -1098,6 +1105,13 @@ class Clause:
for i, s in enumerate(self.immediate_slots):
print('\t\tSlot #%d: %s' % (i, s))
print('\tConstants:')
cnt = 0
for slot in self.immediate_slots:
for const in slot.contents:
print('\t\tConst #%d: 0x%x' % (cnt, const.value))
cnt += 1
if self.data_reg:
print('\tData register: %s' % self.__data_reg)
if not self.is_finished():
......@@ -1122,9 +1136,19 @@ class Clause:
for inst in self.instructions:
inst.reg_file.assign_reg_ports()
const_port = inst.reg_file.const_port
if isinstance(const_port, inst.PendingImmediateSlot):
inst.resolve_immediates(self)
if inst.has_pending_immediates():
pending_slot = inst.reg_file.const_port
# The only slots that should be left are half filled slots that
# couldn't reuse a pre-existing slot
assert pending_slot.bitlen == 32
pending_slot.add_immediate(
ImmediateToken(0, ImmediateToken.ReadType.FULL32))
slot = ImmediateSlot(pending_slot.contents,
len(self.immediate_slots))
inst.resolve_immediates(self, slot)
self.immediate_slots.append(slot)
CLAUSE_START = re.compile(r'^clause_([0-9]+):$')
def scan_clause_start(string):
......
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