Commit f476df2e authored by Alyssa Rosenzweig's avatar Alyssa Rosenzweig 💜

Arrayify GPU

parent 6b3af146
......@@ -918,8 +918,8 @@ trans_emit_for_draw(struct panfrost_context *ctx)
struct panfrost_resource *rsrc = (struct panfrost_resource *) tex_rsrc;
/* Inject the address in. */
ctx->sampler_views[t][i]->hw.swizzled_bitmaps[0] = rsrc->gpu;
ctx->sampler_views[t][i]->hw.swizzled_bitmaps[1] = rsrc->gpu;
ctx->sampler_views[t][i]->hw.swizzled_bitmaps[0] = rsrc->gpu[0];
ctx->sampler_views[t][i]->hw.swizzled_bitmaps[1] = rsrc->gpu[0];
trampolines[i] = panfrost_upload(&ctx->cmdstream, &ctx->sampler_views[t][0]->hw, sizeof(struct mali_texture_descriptor), false);
}
......@@ -1994,7 +1994,7 @@ panfrost_tile_texture(struct panfrost_context *ctx, struct panfrost_resource *rs
/* Allocate the transfer given that known size but do not copy */
uint8_t *swizzled = panfrost_allocate_transfer(&ctx->textures, swizzled_sz, &rsrc->gpu);
uint8_t *swizzled = panfrost_allocate_transfer(&ctx->textures, swizzled_sz, &rsrc->gpu[0]);
/* Run actual texture swizzle, writing directly to the mapped GPU chunk
* we allocated */
......
......@@ -207,7 +207,7 @@ struct panfrost_resource {
* points to the GPU-side, tiled texture, while cpu points to the
* CPU-side, untiled texture from mesa */
mali_ptr gpu;
mali_ptr gpu[MAX_MIP_LEVELS];
struct sw_displaytarget *dt;
};
......
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