Commit 9154d763 authored by Lyude Paul's avatar Lyude Paul

wip: fixes for register file I need to document

p3 == p2 if only writing to p2 and not reading from p3!
parent 5c6a8d60
......@@ -46,7 +46,8 @@ class OpParserBase:
""" Base for op parser classes """
class Op:
def __init__(self, name, opcode, srcs):
def __init__(self, bitlen, name, opcode, srcs):
self.bitlen = bitlen
self.name = name
self.opcode = opcode
self.srcs = srcs
......@@ -59,7 +60,7 @@ class OpParserBase:
return [s.encode_src() for s in self.srcs]
def __repr__(self):
return '<%s at %s; srcs=%s>' % (self.name, hex(id(self)), self.srcs)
return '<%s at %x; srcs=%s>' % (self.name, id(self), self.srcs)
class SrcCountException(ParsingException):
def __init__(self, expected, got):
......@@ -69,12 +70,13 @@ class OpParserBase:
if self.src_cnt and len(srcs) != self.src_cnt:
raise self.SrcCountException(self.src_cnt, len(srcs))
return self.Op(self.name, self.opcode, srcs)
return self.Op(self.bitlen, self.name, self.opcode, srcs)
def __init__(self, name, opcode, src_cnt=None):
self.name = name
self.opcode = opcode
self.src_cnt = src_cnt
if src_cnt:
self.src_cnt = src_cnt
class SrcOpParserBase(OpParserBase):
""" Base class for creating parsers for simple N src ops """
......@@ -98,7 +100,6 @@ class SrcOpParserBase(OpParserBase):
class fma:
NAME = 'FMA'
DST_MNEMONIC = 'T0'
BITLEN = 23
class ZeroSrc():
encoded = bitstring.pack('uint:3=3')
......@@ -108,12 +109,7 @@ class fma:
return cls.encoded
class OpParser(OpParserBase):
def __init_subclass__(cls, **kwargs):
super().__init_subclass__(**kwargs)
class Op(cls.Op):
bitlen = 23
cls.Op = Op
bitlen = 23
class SrcOpParser(OpParser, SrcOpParserBase):
pass
......@@ -308,19 +304,12 @@ class add:
DST_MNEMONIC = 'T1'
class OpParser(OpParserBase):
bitlen = 20
def __init__(self, name, opcode, src_cnt=None, has_data_reg=False):
self.has_data_reg = has_data_reg
super().__init__(name, opcode, src_cnt)
def __init_subclass__(cls, **kwargs):
super().__init_subclass__(**kwargs)
class Op(cls.Op):
bitlen = 20
cls.Op = Op
def parse_op(self, reg_file, srcs):
return super().parse_op(reg_file, srcs)
class SrcOpParser(OpParser, SrcOpParserBase):
pass
......@@ -341,7 +330,7 @@ class add:
class ATestOpParser(SrcOpParser):
def parse_op(self, reg_file, srcs):
reg_file.const_port = 5
reg_file.const_port = Bits(length=8, uint=5)
return super().parse_op(reg_file, srcs)
class LoadAttrOpParser(OpParser):
......@@ -364,7 +353,7 @@ class add:
class BlendDescriptor:
def encode_const_field(self):
return 0x8 | self.idx
return Bits(length=8, uint=0x8 | self.idx)
def __init__(self, idx):
self.idx = idx
......@@ -705,6 +694,7 @@ class RegisterFile:
FIRST_WRITE_FMA_P2 = 9
NONE = 11
FIRST_READ_P3 = 12
FIRST_WRITE_ADD_P2 = 13
WRITE_FMA_P2_ADD_P3 = 15
class NotEnoughPorts(ParsingException):
......@@ -835,8 +825,8 @@ class RegisterFile:
def encode(self, instruction):
const_port = self.const_port
if const_port is None:
const_field = 0
elif isinstance(const_port, int):
const_field = Bits(length=8, uint=0)
elif isinstance(const_port, Bits):
const_field = const_port
else:
const_field = const_port.encode_const_field()
......@@ -859,6 +849,8 @@ class RegisterFile:
if self.ports[3]:
control_field = self.ControlField.WRITE_ADD_P2_READ_P3
elif instruction.first:
control_field = self.ControlField.FIRST_WRITE_ADD_P2
else:
control_field = self.ControlField.WRITE_ADD_P2
......@@ -881,12 +873,17 @@ class RegisterFile:
else:
port_fields[idx] = 0
# When not using port 3 for reading or writing, the compiler always
# seems to set it's port index to the same value as port 2's index.
if not self.ports[3]:
port_fields[3] = port_fields[2]
if self.ports[1]:
if port_fields[0] > port_fields[1]:
for port, idx in enumerate(port_fields[0:1]):
port_fields[idx] = abs(port_fields[idx] - 63)
return bitstring.pack('uint:4, uint:6, uint:5, uint:6, uint:6, uint:8',
return bitstring.pack('uint:4, uint:6, uint:5, uint:6, uint:6, bits:8',
control_field,
port_fields[1],
port_fields[0],
......@@ -894,9 +891,9 @@ class RegisterFile:
port_fields[2],
const_field)
else:
return bitstring.pack('uint:4=0, uint:4, bool, uint:6, uint:6, uint:6, uint:8',
return bitstring.pack('uint:4=0, uint:4, bool, uint:6, uint:6, uint:6, bits:8',
control_field,
self.ports[0] is None,
not bool(self.ports[0]),
port_fields[0],
port_fields[3],
port_fields[2],
......@@ -921,7 +918,7 @@ class ConstantSrc:
class ImmediateZeroSlot:
@classmethod
def encode_const_field(cls):
return 0
return Bits(length=8, uint=0)
@classmethod
def get_src(cls, token):
......@@ -947,8 +944,16 @@ class ImmediateSlot:
else:
return ConstantSrc(token.read_type == ImmediateToken.ReadType.HIGH64)
def encode_contents(self):
return sum(Bits(length=t.bitlen, uint=t.value) for t in self.contents)
def encode_const_field(self):
return self.IDX_MAP[self.idx] << 4
# return bitstring.pack('bits:4, uint:3, uint:1=0',
# self.encode_contents()[60:64],
# self.IDX_MAP[self.idx])
return bitstring.pack('uint:1=0, uint:3, bits:4',
self.IDX_MAP[self.idx],
self.encode_contents()[60:64])
def __repr__(self):
return "<ImmediateSlot #%d at 0x%x; contents=%s>" % (
......@@ -966,7 +971,7 @@ class Uniform:
return ConstantSrc(token.high32)
def encode_const_field(self):
return 0x80 | self.idx
return bitstring.pack('uint:1=1, uint:7', self.idx)
def canonical_idx_str(self):
canonical_idx = self.idx * 2
......
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