Commit 68dd22dd authored by Lyude Paul's avatar Lyude Paul

more wip: don't invert register file

parent 4b306387
......@@ -850,21 +850,21 @@ class RegisterFile:
for port, idx in enumerate(port_fields[0:1]):
port_fields[idx] = abs(port_fields[idx] - 63)
return bitstring.pack('uint:8, uint:6, uint:6, uint:5, uint:6, uint:4',
const_field,
port_fields[2],
port_fields[3],
port_fields[0],
return bitstring.pack('uint:4, uint:6, uint:5, uint:6 , uint:6, uint:8',
control_field,
port_fields[1],
control_field)
else:
return bitstring.pack('uint:8, uint:6, uint:6, uint:6, bool, uint:4, uint:4=0',
const_field,
port_fields[2],
port_fields[3],
port_fields[0],
port_fields[3],
port_fields[2],
const_field)
else:
return bitstring.pack('uint:4=0, uint:4, bool, uint:6, uint:6, uint:6, uint:8',
control_field,
reg_file.ports[0] is None,
control_field)
port_fields[0],
port_fields[3],
port_fields[2],
const_field)
class ConstantSrc:
def __init__(self, high32):
......
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