Commit 5c6a8d60 authored by Lyude Paul's avatar Lyude Paul

wip: Add ATEST parsing

Look at how much easier this is! yay
parent e8ea680a
......@@ -339,6 +339,11 @@ class add:
class Fcmp16OpParser(OpParser):
src_cnt = 2
class ATestOpParser(SrcOpParser):
def parse_op(self, reg_file, srcs):
reg_file.const_port = 5
return super().parse_op(reg_file, srcs)
class LoadAttrOpParser(OpParser):
pass
......@@ -530,9 +535,9 @@ class add:
# since that doesn't need to read from any memory, and then written again
# later based on the result of the stencil and depth tests using the
# special register.
"ATEST.f32" : SrcOpParser("ATEST.f32", 0x191e8, 2, True),
"ATEST.X.f16" : SrcOpParser("ATEST.X.f16", 0x191f0, 2, True),
"ATEST.Y.f16" : SrcOpParser("ATEST.Y.f16", 0x191f8, 2, True),
"ATEST.f32" : ATestOpParser("ATEST.f32", 0x191e8, 2, True),
"ATEST.X.f16" : ATestOpParser("ATEST.X.f16", 0x191f0, 2, True),
"ATEST.Y.f16" : ATestOpParser("ATEST.Y.f16", 0x191f8, 2, True),
# store a varying given the address and datatype from LD_VAR_ADDR
"ST_VAR.v1" : SrcOpParser("ST_VAR.v1", 0x19300, 3, True),
"ST_VAR.v2" : SrcOpParser("ST_VAR.v2", 0x19340, 3, True),
......@@ -829,10 +834,12 @@ class RegisterFile:
def encode(self, instruction):
const_port = self.const_port
if const_port:
const_field = const_port.encode_const_field()
else:
if const_port is None:
const_field = 0
elif isinstance(const_port, int):
const_field = const_port
else:
const_field = const_port.encode_const_field()
# Figure out the value of the control field
if instruction.writes[fma]:
......
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