Commit 5816c901 authored by Lyude Paul's avatar Lyude Paul

more wip

parent 7a7d2c2c
......@@ -114,10 +114,55 @@ class Constants(dict):
self[src] = reg_num
return self[src]
class Register(int):
pass
class Uniform(int):
pass
class OpResult(Enum):
PREV_FMA = 'T0'
PREV_ADD = 'T1'
THIS_FMA = 'T'
class Ports:
class NotEnoughPorts(ParsingException):
def __init__(self, type_, target):
super().__init__('Not enough %s ports for %s' % (type_, target))
def __init__(self):
self.reads = []
self.writes = []
def add_read(self, target):
read_cnt = len(self.reads)
if read_cnt == 3:
raise self.NotEnoughPorts('read', target)
if read_cnt == 2:
# Make sure the read/write port (#3) isn't already being used
# for a write
if len(self.writes) == 2:
raise self.NotEnoughPorts('read', target)
self.reads.append(target)
def add_write(self, target):
write_cnt = len(self.writes)
if write_cnt == 2:
raise self.NotEnoughPorts('write', target)
if write_cnt == 1:
# Make sure the read/write port (#3) isn't already being used
# for a read
if len(self.reads) == 3:
raise self.NotEnoughPorts('write', target)
self.writes.append(target)
CONSTANT_SRC = re.compile(r'^(0x[0-9a-fA-F]+)|[0-9]+$')
CLAUSE_SRC = re.compile(r'^clause_([0-9]+)$')
SPECIAL_SRC = re.compile(r'^(location)\s*:\s*([0-9]+)$')
PORT_SRC = re.compile(r'^([RUT])([0-9]*)$')
CLAUSE_SRC = re.compile(r'^clause_([0-9]+)$')
SPECIAL_SRC = re.compile(r'^(location)\s*:\s*([0-9]+)$')
PORT_SRC = re.compile(r'^([RU])([0-9]+)$')
RESULT_SRC = re.compile(r'^T[01]?$')
def scan_src_arg(string):
match = CONSTANT_SRC.match(string)
if match:
......@@ -141,31 +186,31 @@ def scan_src_arg(string):
raise ParsingException('Invalid argument to %s: %s' % (
match.group(1), match.group(2))) from e
match = RESULT_SRC.match(string)
if match:
return OpResult(match.string)
match = PORT_SRC.match(string)
if not match:
raise ParsingException('Invalid src %s' % string)
type_ = match.group(1)
if type_ == 'T':
idx = match.group(2)
if idx:
if idx == '0':
return (type_, 0)
elif idx == '1':
return (type_, 1)
else:
raise ParsingException("Invalid index for T: %s (index must be 0 or 1)" % (
idx))
else:
return (type_, None)
else:
try:
return (type_, int(match.group(2)))
except TypeError as e:
raise ParsingException('%s without index' % type_) from e
except ValueError as e:
raise ParsingException('Invalid index for %s: %s' % (
type_, match.group(2))) from e
return (match.group(1), int(match.group(2)))
# type_ = match.group(1)
# if type_ == 'T':
# idx = match.group(2)
# if idx:
# if idx != '0':
# return (type_, 0)
# elif idx == '1':
# return (type_, 1)
# else:
# raise ParsingException("Invalid index for T: %s (index must be 0 or 1)" % (
# idx))
# else:
# return (type_, None)
# else:
# return (type_, int(match.group(2)))
def parse_op_dst(string):
......@@ -202,8 +247,7 @@ def scan_op_tokens(string):
elif DST_NO_OUT.match(dst):
dst = (None, dst)
else:
raise ParsingException('In %s: %s is not a valid dst argument' % (
string, dst))
raise ParsingException('%s is not a valid dst argument' % (string, dst))
# Split args
try:
......@@ -450,6 +494,7 @@ try:
current_stage = fma if len(inst_stages) == 0 else add
# Translate the current instruction line into tokens
inst, dst, srcs = scan_op_tokens(l)
if dst[1] != current_stage.DST_MNEMONIC:
raise ParsingException("Expected %s instruction (dst should be %s, got %s)" % (
......@@ -462,6 +507,9 @@ try:
if isinstance(src, int) and src != 0:
srcs[idx] = cycle_consts.assign(src)
# Process uniforms, registers, and special srcs (like location:)
# elif isinstance(src, tuple):
inst_stages.append((inst, dst, srcs))
if current_stage is add:
# Full instruction cycle
......
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