Commit 3b3c7e6c authored by Lyude Paul's avatar Lyude Paul

wip: Add support for uniforms and fix opcode order

The constant mystery is still unsolved, but I'm going to solve that at a
later point after I get some feedback and am sure that what I'm seeing
isn't something to do with the quadword paking algorithm

Additionally: I've fixed up the opcode order, which was reversed (but I
never noticed it since most instructions in my samples didn't have more
than one or two srcs)
parent f98fd720
......@@ -96,7 +96,7 @@ class fma:
def encode(self):
bs = bitstring.BitStream()
bs += bitstring.pack('uint:%d' % (23 - len(bs)), self.opcode)
for src in self.srcs:
for src in reversed(self.srcs):
bs += src.encode_src()
return bs
......@@ -307,7 +307,7 @@ class add:
def encode(self):
bs = bitstring.BitStream()
bs += bitstring.pack('uint:%d' % (20 - len(bs)), self.opcode)
for src in self.srcs:
for src in reversed(self.srcs):
bs += src.encode_src()
return bs
......@@ -583,9 +583,13 @@ class UniformToken:
self.idx = idx
self.high32 = high32
@property
def canonical_idx(self):
return (self.idx * 2) + int(self.high32)
def __repr__(self):
return '<UniformToken %d (%s)>' % (
self.idx, 'High32' if self.high32 else 'Low32')
self.canonical_idx, 'High32' if self.high32 else 'Low32')
class ImmediateToken:
class ReadType(Enum):
......@@ -852,14 +856,26 @@ class ImmediateSlot:
return "<ImmediateSlot #%d at 0x%x; contents=%s>" % (
self.idx, id(self), self.contents)
class Uniform(ConstantSrc):
def __init__(self, high32, idx):
super().__init__(high32)
class Uniform:
def __init__(self, idx):
self.idx = idx
def get_src(self, token):
if token.idx != self.idx:
raise ParsingException("Can't read from uniform %d, const port already being used for uniforms %s" % (
token.canonical_idx, self.canonical_idx_str()))
return ConstantSrc(token.high32)
def encode(self):
return bitstring.pack('uint:1=1, uint:7', self.idx)
def canonical_idx_str(self):
canonical_idx = self.idx * 2
return "%d&%d" % (canonical_idx, canonical_idx + 1)
def __repr__(self):
return '<Uniform %d at 0x%x (%s)>' % (
self.idx, id(self), self.read_kind)
return "<Uniform %s at 0x%x>" % (self.canonical_idx_str(), id(self))
class Clause:
class DataRegister:
......@@ -948,6 +964,14 @@ class Clause:
return isinstance(self.reg_file.const_port,
self.PendingImmediateSlot)
def add_uniform(self, token):
const_port = self.reg_file.const_port
if not isinstance(const_port, Uniform):
const_port = Uniform(token.idx)
self.reg_file.const_port = const_port
return const_port.get_src(token)
@property
def pending_stage(self):
if self.fma is None:
......@@ -1044,6 +1068,9 @@ class Clause:
elif isinstance(src, ImmediateToken):
inst.add_pending_immediate(src)
elif isinstance(src, UniformToken):
srcs[i] = inst.add_uniform(src)
stage = inst.pending_stage
parser = stage.OP_MAP[op]
if stage is fma:
......
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