Commit 227dbb54 authored by Connor Abbott's avatar Connor Abbott Committed by Lyude Paul

bifrost/asm: Fix port0/port1 R32-R63 twiddling

This could never work as-is, since the decoding algorithm as implemented
in SPD has the property that after decoding, port1 > port0 always. If
port0 > port1 initially, then the decoder will compute the final port0
as 63 - port0 and port1 as 63 - port1, making the final port1 larger
than port0. The new encoding algorithm here is the one that I had in
mind initially after RE'ing this.
parent f7c2e51a
......@@ -840,19 +840,12 @@ class RegisterFile:
self._set_reg_port(2, write_regs[0])
if len(read_regs) == 2:
if all(r.idx > 31 for r in read_regs):
big_port = 0
small_port = 1
big_port = 1
small_port = 0
if read_regs[0].idx < read_regs[1].idx:
self._set_reg_port(small_port, read_regs.pop(0))
self._set_reg_port(0, read_regs.pop(0))
self._set_reg_port(small_port, read_regs.pop(1))
self._set_reg_port(0, read_regs.pop(1))
self._set_reg_port(big_port, read_regs.pop())
self._set_reg_port(1, read_regs.pop())
elif len(read_regs) == 1:
self._set_reg_port(0, read_regs.pop())
......@@ -915,9 +908,15 @@ class RegisterFile:
port_fields[2] = port_fields[3]
if self.ports[1]:
if port_fields[0] > port_fields[1]:
if port_fields[0] > 31:
# We made sure when assigning ports that port_fields[1] >
# port_fields[0]. By subtracting both from 63, we will have
# that port_fields[0] > port_fields[1], which will cause the
# decoder to make the exact opposite transform and get back the
# original register indices. Also, the new port_fields[0] will
# be less than 31, so it will fit in 5 bits.
for port, idx in enumerate(port_fields[0:1]):
port_fields[idx] = abs(port_fields[idx] - 63)
port_fields[idx] = 63 - port_fields[idx]
return bitstring.pack('uint:4, uint:6, uint:5, uint:6, uint:6, bits:8',
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