...
 
Commits (164)
......@@ -132,6 +132,7 @@ with_gallium_r300 = false
with_gallium_r600 = false
with_gallium_nouveau = false
with_gallium_freedreno = false
with_gallium_panfrost = false
with_gallium_softpipe = false
with_gallium_vc4 = false
with_gallium_vc5 = false
......@@ -149,7 +150,7 @@ if _drivers == 'auto'
if ['x86', 'x86_64'].contains(host_machine.cpu_family())
_drivers = 'r300,r600,radeonsi,nouveau,virgl,svga,swrast'
elif ['arm', 'aarch64'].contains(host_machine.cpu_family())
_drivers = 'pl111,vc4,vc5,freedreno,etnaviv,imx,nouveau,tegra,virgl,svga,swrast'
_drivers = 'pl111,vc4,vc5,panfrost,freedreno,etnaviv,imx,nouveau,tegra,virgl,svga,swrast'
else
error('Unknown architecture. Please pass -Dgallium-drivers to set driver options. Patches gladly accepted to fix this.')
endif
......@@ -167,6 +168,7 @@ if _drivers != ''
with_gallium_r600 = _split.contains('r600')
with_gallium_nouveau = _split.contains('nouveau')
with_gallium_freedreno = _split.contains('freedreno')
with_gallium_panfrost = _split.contains('panfrost')
with_gallium_softpipe = _split.contains('swrast')
with_gallium_vc4 = _split.contains('vc4')
with_gallium_vc5 = _split.contains('vc5')
......
......@@ -1888,6 +1888,7 @@ typedef struct nir_shader_compiler_options {
bool lower_extract_word;
bool lower_all_io_to_temps;
bool lower_fsinpi;
/**
* Does the driver support real 32-bit integers? (Otherwise, integers
......
......@@ -214,6 +214,8 @@ unop("fquantize2f16", tfloat, "(fabs(src0) < ldexpf(1.0, -14)) ? copysignf(0.0f,
unop("fsin", tfloat, "bit_size == 64 ? sin(src0) : sinf(src0)")
unop("fcos", tfloat, "bit_size == 64 ? cos(src0) : cosf(src0)")
unop("fsinpi", tfloat, "bit_size == 64 ? sin(src0 / 3.14159) : sinf(src0 / 3.14159)")
unop("fcospi", tfloat, "bit_size == 64 ? cos(src0 / 3.14159) : cosf(src0 / 3.14159)")
# Partial derivatives.
......
......@@ -562,6 +562,9 @@ optimizations = [
('extract_i8', 'v', 3))),
127.0))),
'options->lower_unpack_snorm_4x8'),
(('fsin', a), ('fsinpi', ('fdiv', a, 3.14159)), 'options->lower_fsinpi'),
(('fcos', a), ('fcospi', ('fdiv', a, 3.14159)), 'options->lower_fsinpi'),
]
invert = {'feq': 'fne', 'fne': 'feq', 'fge': 'flt', 'flt': 'fge' }
......
midgard_compiler = executable(
'midgard_compiler',
'midgard/midgard_cmdline.c',
include_directories : [inc_common, inc_src, inc_include, inc_gallium, inc_gallium_aux, include_directories('midgard')],
dependencies : [
dep_thread,
idep_nir
],
link_with : [
libgallium,
libglsl_standalone,
libmesa_util
],
build_by_default : true
)
/* Author(s):
* Connor Abbott
* Alyssa Rosenzweig
*
* Copyright (c) 2013 Connor Abbott (connor@abbott.cx)
* Copyright (c) 2018 Alyssa Rosenzweig (alyssa@rosenzweig.io)
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
/* midgard.h - definitions for the Midgard shader architecture */
typedef unsigned midgard_word_type;
typedef enum
{
midgard_alu_vmul,
midgard_alu_sadd,
midgard_alu_smul,
midgard_alu_vadd,
midgard_alu_lut
} midgard_alu_e;
/*
* ALU words
*/
typedef enum
{
midgard_alu_op_fadd = 0x10,
midgard_alu_op_fmul = 0x14,
midgard_alu_op_fmin = 0x28,
midgard_alu_op_fmax = 0x2C,
midgard_alu_op_fmov = 0x30,
midgard_alu_op_ffloor = 0x36,
midgard_alu_op_fceil = 0x37,
midgard_alu_op_fdot3 = 0x3C,
midgard_alu_op_fdot3r = 0x3D,
midgard_alu_op_fdot4 = 0x3E,
midgard_alu_op_freduce = 0x3F,
midgard_alu_op_iadd = 0x40,
midgard_alu_op_isub = 0x46,
midgard_alu_op_imul = 0x58,
midgard_alu_op_imov = 0x7B,
midgard_alu_op_feq = 0x80,
midgard_alu_op_fne = 0x81,
midgard_alu_op_flt = 0x82,
midgard_alu_op_fle = 0x83,
midgard_alu_op_f2i = 0x99,
midgard_alu_op_ieq = 0xA0,
midgard_alu_op_ine = 0xA1,
midgard_alu_op_ilt = 0xA4,
midgard_alu_op_ile = 0xA5,
midgard_alu_op_ball = 0xA9,
midgard_alu_op_bany = 0xB1,
midgard_alu_op_i2f = 0xB8,
midgard_alu_op_csel = 0xC5,
midgard_alu_op_fatan_pt2 = 0xE8,
midgard_alu_op_frcp = 0xF0,
midgard_alu_op_frsqrt = 0xF2,
midgard_alu_op_fsqrt = 0xF3,
midgard_alu_op_fexp2 = 0xF4,
midgard_alu_op_flog2 = 0xF5,
midgard_alu_op_fsin = 0xF6,
midgard_alu_op_fcos = 0xF7,
midgard_alu_op_fatan_pt1 = 0xF9,
} midgard_alu_op_e;
typedef enum
{
midgard_outmod_none = 0,
midgard_outmod_pos = 1,
midgard_outmod_int = 2,
midgard_outmod_sat = 3
} midgard_outmod_e;
typedef enum
{
midgard_reg_mode_half = 1,
midgard_reg_mode_full = 2
} midgard_reg_mode_e;
typedef enum
{
midgard_dest_override_lower = 0,
midgard_dest_override_upper = 1,
midgard_dest_override_none = 2
} midgard_dest_override_e;
typedef struct
__attribute__((__packed__))
{
bool abs : 1;
bool negate : 1;
/* replicate lower half if dest = half, or low/high half selection if
* dest = full
*/
bool rep_low : 1;
bool rep_high : 1; /* unused if dest = full */
bool half : 1; /* only matters if dest = full */
unsigned swizzle : 8;
} midgard_vector_alu_src_t;
typedef struct
__attribute__((__packed__))
{
midgard_alu_op_e op : 8;
midgard_reg_mode_e reg_mode : 2;
unsigned src1 : 13;
unsigned src2 : 13;
midgard_dest_override_e dest_override : 2;
midgard_outmod_e outmod : 2;
unsigned mask : 8;
} midgard_vector_alu_t;
typedef struct
__attribute__((__packed__))
{
bool abs : 1;
bool negate : 1;
bool full : 1; /* 0 = half, 1 = full */
unsigned component : 3;
} midgard_scalar_alu_src_t;
typedef struct
__attribute__((__packed__))
{
midgard_alu_op_e op : 8;
unsigned src1 : 6;
unsigned src2 : 11;
unsigned unknown : 1;
midgard_outmod_e outmod : 2;
bool output_full : 1;
unsigned output_component : 3;
} midgard_scalar_alu_t;
/* ALU control words are single bit fields with a lot of space */
#define ALU_ENAB_VEC_MUL (1 << 17)
#define ALU_ENAB_SCAL_ADD (1 << 19)
#define ALU_ENAB_VEC_ADD (1 << 21)
#define ALU_ENAB_SCAL_MUL (1 << 23)
#define ALU_ENAB_VEC_LUT (1 << 25)
#define ALU_ENAB_BR_COMPACT (1 << 26)
#define ALU_ENAB_BRANCH (1 << 27)
/* Vector-independant shorthands for the above; these numbers are arbitrary and
* not from the ISA. Convert to the above with unit_enum_to_midgard */
#define UNIT_MUL 0
#define UNIT_ADD 1
#define UNIT_LUT 2
/* ALU register fields are weird because of inline constants */
typedef struct
__attribute__((__packed__))
{
unsigned input1_reg : 5;
unsigned input2_reg : 5;
unsigned output_reg : 5;
unsigned inline_2 : 1;
} alu_register_word;
typedef struct
__attribute__((__packed__))
{
unsigned src1_reg : 5;
unsigned src2_reg : 5;
unsigned out_reg : 5;
bool src2_imm : 1;
} midgard_reg_info_t;
/* Compact writeouts */
typedef enum
{
midgard_jmp_writeout_op_branch_uncond = 1,
midgard_jmp_writeout_op_branch_cond = 2,
midgard_jmp_writeout_op_writeout = 7,
} midgard_jmp_writeout_op_e;
typedef struct
__attribute__((__packed__))
{
midgard_jmp_writeout_op_e op : 3; /* == branch_uncond */
unsigned dest_tag : 4; /* tag of branch destination */
unsigned unknown : 2;
int offset : 7;
} midgard_branch_uncond_t;
typedef struct
__attribute__((__packed__))
{
midgard_jmp_writeout_op_e op : 3; /* == branch_cond */
unsigned dest_tag : 4; /* tag of branch destination */
int offset : 7;
unsigned cond : 2;
} midgard_branch_cond_t;
/*
* Load/store words
*/
#define OP_IS_STORE(op) (\
op == midgard_op_store_vary_16 || \
op == midgard_op_store_vary_32 \
)
typedef enum
{
midgard_op_ld_st_noop = 0x03,
midgard_op_load_attr_16 = 0x95,
midgard_op_load_attr_32 = 0x94,
midgard_op_load_vary_16 = 0x99,
midgard_op_load_vary_32 = 0x98,
midgard_op_load_uniform_16 = 0xAC,
midgard_op_load_uniform_32 = 0xB0,
midgard_op_store_vary_16 = 0xD5,
midgard_op_store_vary_32 = 0xD4
} midgard_load_store_op_e;
typedef struct
__attribute__((__packed__))
{
midgard_load_store_op_e op : 8;
unsigned reg : 5;
unsigned mask : 4;
unsigned swizzle : 8;
unsigned unknown : 26;
unsigned address : 9;
} midgard_load_store_word_t;
typedef struct
__attribute__((__packed__))
{
uint8_t tag : 8;
uint64_t word1 : 60;
uint64_t word2 : 60;
} midgard_load_store_t;
/* Some defines not found in the disassembler */
/* 4-bit type tags */
#define TAG_TEXTURE_4 0x3
#define TAG_LOAD_STORE_4 0x5
#define TAG_ALU_4 0x8
#define TAG_ALU_8 0x9
#define TAG_ALU_12 0xA
#define TAG_ALU_16 0xB
/* Special register aliases */
#define REGISTER_UNUSED 24
#define REGISTER_CONSTANT 26
#define REGISTER_OFFSET 27
#define REGISTER_VERTEX 27
#define REGISTER_TEXTURE_1 28
#define REGISTER_TEXTURE_2 29
#define REGISTER_SELECT 31
/* SSA helper aliases to mimic the registers. UNUSED_0 encoded as an inline
* constant. UNUSED_1 encoded as REGISTER_UNUSED */
#define SSA_UNUSED_0 0
#define SSA_UNUSED_1 -2
#define SSA_FIXED_SHIFT 24
#define SSA_FIXED_REGISTER(reg) ((1 + reg) << SSA_FIXED_SHIFT)
#define SSA_REG_FROM_FIXED(reg) ((reg >> SSA_FIXED_SHIFT) - 1)
#define SSA_FIXED_MINIMUM SSA_FIXED_REGISTER(0)
/* Should be mapped to REGISTER_VERTEX, eventually */
#define VERTEX_EPILOGUE_BASE 0xDEAD00
/* Swizzle support */
#define SWIZZLE(A, B, C, D) ((D << 6) | (C << 4) | (B << 2) | (A << 0))
#define SWIZZLE_FROM_ARRAY(r) SWIZZLE(r[0], r[1], r[2], r[3])
#define COMPONENT_X 0x0
#define COMPONENT_Y 0x1
#define COMPONENT_Z 0x2
#define COMPONENT_W 0x3
/* Output writing "condition" for the branch (all one's) */
#define COND_FBWRITE 0x3
This diff is collapsed.
......@@ -91,6 +91,11 @@ if with_gallium_freedreno
else
driver_freedreno = declare_dependency()
endif
if with_gallium_panfrost
subdir('drivers/panfrost')
else
driver_panfrost = declare_dependency()
endif
if with_gallium_vc4
subdir('winsys/vc4/drm')
subdir('drivers/vc4')
......