Commit b3d6937f authored by Anuj Phogat's avatar Anuj Phogat

i965/icl: Set Error Detection Behavior Control Bit in L3CNTLREG

The default setting of this bit is not the desirable behavior.
WA_1406697149
Signed-off-by: Anuj Phogat's avatarAnuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin's avatarLionel Landwerlin <lionel.g.landwerlin@intel.com>
parent ac95a0e0
......@@ -1646,6 +1646,7 @@ enum brw_pixel_shader_coverage_mask_mode {
# define GEN8_L3CNTLREG_DC_ALLOC_MASK INTEL_MASK(24, 18)
# define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT 25
# define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25)
# define GEN8_L3CNTLREG_EDBC_NO_HANG (1 << 9)
#define GEN10_CACHE_MODE_SS 0x0e420
#define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4)
......
......@@ -79,6 +79,13 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
brw_load_register_imm32(brw, HALF_SLICE_CHICKEN7,
TEXEL_OFFSET_FIX_MASK |
TEXEL_OFFSET_FIX_ENABLE);
/* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
* in L3CNTLREG register. The default setting of the bit is not the
* desirable behavior.
*/
brw_load_register_imm32(brw, GEN8_L3CNTLREG,
GEN8_L3CNTLREG_EDBC_NO_HANG);
}
if (devinfo->gen == 10 || devinfo->gen == 11) {
......
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