Commit 7b697c8b authored by Marek Olšák's avatar Marek Olšák

amd: move r600d_common.h into r600g

Reviewed-by: default avatarNicolai Hähnle <nicolai.haehnle@amd.com>
parent 76997e91
COMMON_HEADER_FILES = \
common/gfx9d.h \
common/sid.h \
common/r600d_common.h \
common/amd_family.h \
common/amd_kernel_code_t.h \
common/amdgpu_id.h
......
......@@ -3605,7 +3605,7 @@ static void write_event(struct radv_cmd_buffer *cmd_buffer,
cmd_buffer->state.predicating,
cmd_buffer->device->physical_device->rad_info.chip_class,
false,
EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
V_028A90_BOTTOM_OF_PIPE_TS, 0,
1, va, 2, value);
assert(cmd_buffer->cs->cdw <= cdw_max);
......
......@@ -28,7 +28,7 @@
#include <string.h>
#include <stdint.h>
#include <assert.h>
#include "r600d_common.h"
#include "sid.h"
static inline unsigned radeon_check_space(struct radeon_winsys *ws,
struct radeon_winsys_cs *cs,
......@@ -41,11 +41,11 @@ static inline unsigned radeon_check_space(struct radeon_winsys *ws,
static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{
assert(reg < R600_CONTEXT_REG_OFFSET);
assert(reg < SI_CONTEXT_REG_OFFSET);
assert(cs->cdw + 2 + num <= cs->max_dw);
assert(num);
radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2);
radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
}
static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
......@@ -56,11 +56,11 @@ static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned r
static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{
assert(reg >= R600_CONTEXT_REG_OFFSET);
assert(reg >= SI_CONTEXT_REG_OFFSET);
assert(cs->cdw + 2 + num <= cs->max_dw);
assert(num);
radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2);
radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
}
static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
......@@ -74,10 +74,10 @@ static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
unsigned reg, unsigned idx,
unsigned value)
{
assert(reg >= R600_CONTEXT_REG_OFFSET);
assert(reg >= SI_CONTEXT_REG_OFFSET);
assert(cs->cdw + 3 <= cs->max_dw);
radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
radeon_emit(cs, value);
}
......
......@@ -26,7 +26,6 @@
#include "vk_format.h"
#include "sid.h"
#include "r600d_common.h"
#include "vk_util.h"
......@@ -767,7 +766,7 @@ unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap)
#define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == VK_SWIZZLE_##swz)
if (format == VK_FORMAT_B10G11R11_UFLOAT_PACK32)
return V_0280A0_SWAP_STD;
return V_028C70_SWAP_STD;
if (desc->layout != VK_FORMAT_LAYOUT_PLAIN)
return ~0U;
......@@ -775,45 +774,45 @@ unsigned radv_translate_colorswap(VkFormat format, bool do_endian_swap)
switch (desc->nr_channels) {
case 1:
if (HAS_SWIZZLE(0,X))
return V_0280A0_SWAP_STD; /* X___ */
return V_028C70_SWAP_STD; /* X___ */
else if (HAS_SWIZZLE(3,X))
return V_0280A0_SWAP_ALT_REV; /* ___X */
return V_028C70_SWAP_ALT_REV; /* ___X */
break;
case 2:
if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
(HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
(HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
return V_0280A0_SWAP_STD; /* XY__ */
return V_028C70_SWAP_STD; /* XY__ */
else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
(HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
(HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
/* YX__ */
return (do_endian_swap ? V_0280A0_SWAP_STD : V_0280A0_SWAP_STD_REV);
return (do_endian_swap ? V_028C70_SWAP_STD : V_028C70_SWAP_STD_REV);
else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
return V_0280A0_SWAP_ALT; /* X__Y */
return V_028C70_SWAP_ALT; /* X__Y */
else if (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(3,X))
return V_0280A0_SWAP_ALT_REV; /* Y__X */
return V_028C70_SWAP_ALT_REV; /* Y__X */
break;
case 3:
if (HAS_SWIZZLE(0,X))
return (do_endian_swap ? V_0280A0_SWAP_STD_REV : V_0280A0_SWAP_STD);
return (do_endian_swap ? V_028C70_SWAP_STD_REV : V_028C70_SWAP_STD);
else if (HAS_SWIZZLE(0,Z))
return V_0280A0_SWAP_STD_REV; /* ZYX */
return V_028C70_SWAP_STD_REV; /* ZYX */
break;
case 4:
/* check the middle channels, the 1st and 4th channel can be NONE */
if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z)) {
return V_0280A0_SWAP_STD; /* XYZW */
return V_028C70_SWAP_STD; /* XYZW */
} else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y)) {
return V_0280A0_SWAP_STD_REV; /* WZYX */
return V_028C70_SWAP_STD_REV; /* WZYX */
} else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X)) {
return V_0280A0_SWAP_ALT; /* ZYXW */
return V_028C70_SWAP_ALT; /* ZYXW */
} else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,W)) {
/* YZWX */
if (desc->is_array)
return V_0280A0_SWAP_ALT_REV;
return V_028C70_SWAP_ALT_REV;
else
return (do_endian_swap ? V_0280A0_SWAP_ALT : V_0280A0_SWAP_ALT_REV);
return (do_endian_swap ? V_028C70_SWAP_ALT : V_028C70_SWAP_ALT_REV);
}
break;
}
......
......@@ -40,7 +40,6 @@
#include "sid.h"
#include "gfx9d.h"
#include "r600d_common.h"
#include "ac_binary.h"
#include "ac_llvm_util.h"
#include "ac_nir_to_llvm.h"
......
......@@ -1153,7 +1153,7 @@ void radv_CmdEndQuery(
false,
cmd_buffer->device->physical_device->rad_info.chip_class,
false,
EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0,
V_028A90_BOTTOM_OF_PIPE_TS, 0,
1, avail_va, 0, 1);
break;
default:
......
......@@ -39,7 +39,6 @@
#include "sid.h"
#include "gfx9d.h"
#include "r600d_common.h"
#include "ac_binary.h"
#include "ac_llvm_util.h"
#include "ac_nir_to_llvm.h"
......
......@@ -32,7 +32,6 @@
#include <string.h>
#include <stdint.h>
#include <assert.h>
#include "r600d_common.h"
#include <amdgpu.h>
#include "radv_radeon_winsys.h"
......
C_SOURCES = \
r600d_common.h \
compute_memory_pool.c \
compute_memory_pool.h \
eg_asm.c \
......
......@@ -31,7 +31,7 @@
#define R600_CS_H
#include "r600_pipe_common.h"
#include "amd/common/r600d_common.h"
#include "r600d_common.h"
/**
* Return true if there is enough memory in VRAM and GTT for the buffers
......
......@@ -28,7 +28,7 @@
#include "util/u_memory.h"
#include "r600_query.h"
#include "r600_pipe_common.h"
#include "amd/common/r600d_common.h"
#include "r600d_common.h"
/* Max counters per HW block */
#define R600_QUERY_MAX_COUNTERS 16
......
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