Commit 76997e91 authored by Marek Olšák's avatar Marek Olšák

radeonsi: shrink r600d_common.h and stop using it

Reviewed-by: default avatarNicolai Hähnle <nicolai.haehnle@amd.com>
parent 0ecf9b90
This diff is collapsed.
...@@ -113,6 +113,13 @@ ...@@ -113,6 +113,13 @@
#define PKT3_INDIRECT_BUFFER_SI 0x32 /* not on CIK */ #define PKT3_INDIRECT_BUFFER_SI 0x32 /* not on CIK */
#define PKT3_INDIRECT_BUFFER_CONST 0x33 #define PKT3_INDIRECT_BUFFER_CONST 0x33
#define PKT3_STRMOUT_BUFFER_UPDATE 0x34 #define PKT3_STRMOUT_BUFFER_UPDATE 0x34
#define STRMOUT_STORE_BUFFER_FILLED_SIZE 1
#define STRMOUT_OFFSET_SOURCE(x) (((unsigned)(x) & 0x3) << 1)
#define STRMOUT_OFFSET_FROM_PACKET 0
#define STRMOUT_OFFSET_FROM_VGT_FILLED_SIZE 1
#define STRMOUT_OFFSET_FROM_MEM 2
#define STRMOUT_OFFSET_NONE 3
#define STRMOUT_SELECT_BUFFER(x) (((unsigned)(x) & 0x3) << 8)
#define PKT3_DRAW_INDEX_OFFSET_2 0x35 #define PKT3_DRAW_INDEX_OFFSET_2 0x35
#define PKT3_WRITE_DATA 0x37 #define PKT3_WRITE_DATA 0x37
#define R_370_CONTROL 0x370 /* 0x[packet number][word index] */ #define R_370_CONTROL 0x370 /* 0x[packet number][word index] */
...@@ -137,6 +144,7 @@ ...@@ -137,6 +144,7 @@
#define PKT3_MPEG_INDEX 0x3A /* not on CIK */ #define PKT3_MPEG_INDEX 0x3A /* not on CIK */
#define PKT3_WAIT_REG_MEM 0x3C #define PKT3_WAIT_REG_MEM 0x3C
#define WAIT_REG_MEM_EQUAL 3 #define WAIT_REG_MEM_EQUAL 3
#define WAIT_REG_MEM_MEM_SPACE(x) (((unsigned)(x) & 0x3) << 4)
#define PKT3_MEM_WRITE 0x3D /* not on CIK */ #define PKT3_MEM_WRITE 0x3D /* not on CIK */
#define PKT3_INDIRECT_BUFFER_CIK 0x3F /* new on CIK */ #define PKT3_INDIRECT_BUFFER_CIK 0x3F /* new on CIK */
#define R_3F0_IB_BASE_LO 0x3F0 #define R_3F0_IB_BASE_LO 0x3F0
...@@ -156,6 +164,7 @@ ...@@ -156,6 +164,7 @@
#define COPY_DATA_IMM 5 #define COPY_DATA_IMM 5
#define COPY_DATA_TIMESTAMP 9 #define COPY_DATA_TIMESTAMP 9
#define COPY_DATA_DST_SEL(x) (((unsigned)(x) & 0xf) << 8) #define COPY_DATA_DST_SEL(x) (((unsigned)(x) & 0xf) << 8)
#define COPY_DATA_MEM_ASYNC 5
#define COPY_DATA_COUNT_SEL (1 << 16) #define COPY_DATA_COUNT_SEL (1 << 16)
#define COPY_DATA_WR_CONFIRM (1 << 20) #define COPY_DATA_WR_CONFIRM (1 << 20)
#define PKT3_PFP_SYNC_ME 0x42 #define PKT3_PFP_SYNC_ME 0x42
...@@ -164,6 +173,14 @@ ...@@ -164,6 +173,14 @@
#define PKT3_COND_WRITE 0x45 #define PKT3_COND_WRITE 0x45
#define PKT3_EVENT_WRITE 0x46 #define PKT3_EVENT_WRITE 0x46
#define PKT3_EVENT_WRITE_EOP 0x47 /* not on GFX9 */ #define PKT3_EVENT_WRITE_EOP 0x47 /* not on GFX9 */
#define EOP_INT_SEL(x) ((x) << 24)
#define EOP_INT_SEL_NONE 0
#define EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM 3
#define EOP_DATA_SEL(x) ((x) << 29)
#define EOP_DATA_SEL_DISCARD 0
#define EOP_DATA_SEL_VALUE_32BIT 1
#define EOP_DATA_SEL_VALUE_64BIT 2
#define EOP_DATA_SEL_TIMESTAMP 3
/* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets /* CP DMA bug: Any use of CP_DMA.DST_SEL=TC must be avoided when EOS packets
* are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and * are used. Use DST_SEL=MC instead. For prefetch, use SRC_SEL=TC and
* DST_SEL=MC. Only CIK chips are affected. * DST_SEL=MC. Only CIK chips are affected.
......
...@@ -525,13 +525,13 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer, ...@@ -525,13 +525,13 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]); radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[0]);
radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]); radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_mask[1]);
radeon_set_context_reg(cmd_buffer->cs, CM_R_028804_DB_EQAA, ms->db_eqaa); radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa);
radeon_set_context_reg(cmd_buffer->cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples) if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
return; return;
radeon_set_context_reg_seq(cmd_buffer->cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2); radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl); radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config); radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
......
...@@ -1071,8 +1071,8 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, ...@@ -1071,8 +1071,8 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) | S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1); S_028A4C_FORCE_EOV_REZ_ENABLE(1);
ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9); ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9);
if (ms->num_samples > 1) { if (ms->num_samples > 1) {
...@@ -1087,7 +1087,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline, ...@@ -1087,7 +1087,7 @@ radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) | ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) | S_028BE0_MAX_SAMPLE_DIST(radv_cayman_get_maxdist(log_samples)) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */ S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
ms->pa_sc_mode_cntl_1 |= EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1); ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
} }
const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order = const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
......
...@@ -1425,25 +1425,25 @@ void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_sampl ...@@ -1425,25 +1425,25 @@ void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_sampl
switch (nr_samples) { switch (nr_samples) {
default: default:
case 1: case 1:
radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0); radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0);
radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0); radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0);
radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0); radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0);
radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0); radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0);
break; break;
case 2: case 2:
radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]); radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]);
radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]); radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]);
radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]); radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]);
radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]); radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]);
break; break;
case 4: case 4:
radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]); radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]);
radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]); radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]);
radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]); radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_4x[2]);
radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]); radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_4x[3]);
break; break;
case 8: case 8:
radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14); radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 14);
radeon_emit(cs, cm_sample_locs_8x[0]); radeon_emit(cs, cm_sample_locs_8x[0]);
radeon_emit(cs, cm_sample_locs_8x[4]); radeon_emit(cs, cm_sample_locs_8x[4]);
radeon_emit(cs, 0); radeon_emit(cs, 0);
...@@ -1460,7 +1460,7 @@ void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_sampl ...@@ -1460,7 +1460,7 @@ void radv_cayman_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_sampl
radeon_emit(cs, cm_sample_locs_8x[7]); radeon_emit(cs, cm_sample_locs_8x[7]);
break; break;
case 16: case 16:
radeon_set_context_reg_seq(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16); radeon_set_context_reg_seq(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 16);
radeon_emit(cs, cm_sample_locs_16x[0]); radeon_emit(cs, cm_sample_locs_16x[0]);
radeon_emit(cs, cm_sample_locs_16x[4]); radeon_emit(cs, cm_sample_locs_16x[4]);
radeon_emit(cs, cm_sample_locs_16x[8]); radeon_emit(cs, cm_sample_locs_16x[8]);
......
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
*/ */
#include "r600_cs.h" #include "r600_cs.h"
#include "evergreend.h"
/* 2xMSAA /* 2xMSAA
* There are two locations (4, 4), (-4, -4). */ * There are two locations (4, 4), (-4, -4). */
......
...@@ -1650,7 +1650,7 @@ static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, ...@@ -1650,7 +1650,7 @@ static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples,
S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */ S_028C00_EXPAND_LINE_WIDTH(1)); /* R_028C00_PA_SC_LINE_CNTL */
radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) | radeon_emit(cs, S_028C04_MSAA_NUM_SAMPLES(util_logbase2(nr_samples)) |
S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */ S_028C04_MAX_SAMPLE_DIST(max_dist)); /* R_028C04_PA_SC_AA_CONFIG */
radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) | EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1)); EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
...@@ -1658,7 +1658,7 @@ static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples, ...@@ -1658,7 +1658,7 @@ static void evergreen_emit_msaa_state(struct r600_context *rctx, int nr_samples,
radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2); radeon_set_context_reg_seq(cs, R_028C00_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */ radeon_emit(cs, S_028C00_LAST_PIXEL(1)); /* R_028C00_PA_SC_LINE_CNTL */
radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */ radeon_emit(cs, 0); /* R_028C04_PA_SC_AA_CONFIG */
radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1)); EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
} }
......
...@@ -201,6 +201,116 @@ ...@@ -201,6 +201,116 @@
/* Registers */ /* Registers */
#define R_0084FC_CP_STRMOUT_CNTL 0x0084FC #define R_0084FC_CP_STRMOUT_CNTL 0x0084FC
#define S_0084FC_OFFSET_UPDATE_DONE(x) (((unsigned)(x) & 0x1) << 0) #define S_0084FC_OFFSET_UPDATE_DONE(x) (((unsigned)(x) & 0x1) << 0)
#define R_028B94_VGT_STRMOUT_CONFIG 0x028B94
#define S_028B94_STREAMOUT_0_EN(x) (((unsigned)(x) & 0x1) << 0)
#define G_028B94_STREAMOUT_0_EN(x) (((x) >> 0) & 0x1)
#define C_028B94_STREAMOUT_0_EN 0xFFFFFFFE
#define S_028B94_STREAMOUT_1_EN(x) (((unsigned)(x) & 0x1) << 1)
#define G_028B94_STREAMOUT_1_EN(x) (((x) >> 1) & 0x1)
#define C_028B94_STREAMOUT_1_EN 0xFFFFFFFD
#define S_028B94_STREAMOUT_2_EN(x) (((unsigned)(x) & 0x1) << 2)
#define G_028B94_STREAMOUT_2_EN(x) (((x) >> 2) & 0x1)
#define C_028B94_STREAMOUT_2_EN 0xFFFFFFFB
#define S_028B94_STREAMOUT_3_EN(x) (((unsigned)(x) & 0x1) << 3)
#define G_028B94_STREAMOUT_3_EN(x) (((x) >> 3) & 0x1)
#define C_028B94_STREAMOUT_3_EN 0xFFFFFFF7
#define S_028B94_RAST_STREAM(x) (((unsigned)(x) & 0x07) << 4)
#define G_028B94_RAST_STREAM(x) (((x) >> 4) & 0x07)
#define C_028B94_RAST_STREAM 0xFFFFFF8F
#define S_028B94_RAST_STREAM_MASK(x) (((unsigned)(x) & 0x0F) << 8) /* SI+ */
#define G_028B94_RAST_STREAM_MASK(x) (((x) >> 8) & 0x0F)
#define C_028B94_RAST_STREAM_MASK 0xFFFFF0FF
#define S_028B94_USE_RAST_STREAM_MASK(x) (((unsigned)(x) & 0x1) << 31) /* SI+ */
#define G_028B94_USE_RAST_STREAM_MASK(x) (((x) >> 31) & 0x1)
#define C_028B94_USE_RAST_STREAM_MASK 0x7FFFFFFF
#define R_028B98_VGT_STRMOUT_BUFFER_CONFIG 0x028B98
#define S_028B98_STREAM_0_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 0)
#define G_028B98_STREAM_0_BUFFER_EN(x) (((x) >> 0) & 0x0F)
#define C_028B98_STREAM_0_BUFFER_EN 0xFFFFFFF0
#define S_028B98_STREAM_1_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 4)
#define G_028B98_STREAM_1_BUFFER_EN(x) (((x) >> 4) & 0x0F)
#define C_028B98_STREAM_1_BUFFER_EN 0xFFFFFF0F
#define S_028B98_STREAM_2_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 8)
#define G_028B98_STREAM_2_BUFFER_EN(x) (((x) >> 8) & 0x0F)
#define C_028B98_STREAM_2_BUFFER_EN 0xFFFFF0FF
#define S_028B98_STREAM_3_BUFFER_EN(x) (((unsigned)(x) & 0x0F) << 12)
#define G_028B98_STREAM_3_BUFFER_EN(x) (((x) >> 12) & 0x0F)
#define C_028B98_STREAM_3_BUFFER_EN 0xFFFF0FFF
#define EG_R_028A4C_PA_SC_MODE_CNTL_1 0x028A4C
#define EG_S_028A4C_PS_ITER_SAMPLE(x) (((unsigned)(x) & 0x1) << 16)
#define EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(x) (((unsigned)(x) & 0x1) << 25)
#define EG_S_028A4C_FORCE_EOV_REZ_ENABLE(x) (((unsigned)(x) & 0x1) << 26)
#define CM_R_028804_DB_EQAA 0x00028804
#define S_028804_MAX_ANCHOR_SAMPLES(x) (((unsigned)(x) & 0x07) << 0)
#define G_028804_MAX_ANCHOR_SAMPLES(x) (((x) >> 0) & 0x07)
#define C_028804_MAX_ANCHOR_SAMPLES 0xFFFFFFF8
#define S_028804_PS_ITER_SAMPLES(x) (((unsigned)(x) & 0x07) << 4)
#define G_028804_PS_ITER_SAMPLES(x) (((x) >> 4) & 0x07)
#define C_028804_PS_ITER_SAMPLES 0xFFFFFF8F
#define S_028804_MASK_EXPORT_NUM_SAMPLES(x) (((unsigned)(x) & 0x07) << 8)
#define G_028804_MASK_EXPORT_NUM_SAMPLES(x) (((x) >> 8) & 0x07)
#define C_028804_MASK_EXPORT_NUM_SAMPLES 0xFFFFF8FF
#define S_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((unsigned)(x) & 0x07) << 12)
#define G_028804_ALPHA_TO_MASK_NUM_SAMPLES(x) (((x) >> 12) & 0x07)
#define C_028804_ALPHA_TO_MASK_NUM_SAMPLES 0xFFFF8FFF
#define S_028804_HIGH_QUALITY_INTERSECTIONS(x) (((unsigned)(x) & 0x1) << 16)
#define G_028804_HIGH_QUALITY_INTERSECTIONS(x) (((x) >> 16) & 0x1)
#define C_028804_HIGH_QUALITY_INTERSECTIONS 0xFFFEFFFF
#define S_028804_INCOHERENT_EQAA_READS(x) (((unsigned)(x) & 0x1) << 17)
#define G_028804_INCOHERENT_EQAA_READS(x) (((x) >> 17) & 0x1)
#define C_028804_INCOHERENT_EQAA_READS 0xFFFDFFFF
#define S_028804_INTERPOLATE_COMP_Z(x) (((unsigned)(x) & 0x1) << 18)
#define G_028804_INTERPOLATE_COMP_Z(x) (((x) >> 18) & 0x1)
#define C_028804_INTERPOLATE_COMP_Z 0xFFFBFFFF
#define S_028804_INTERPOLATE_SRC_Z(x) (((unsigned)(x) & 0x1) << 19)
#define G_028804_INTERPOLATE_SRC_Z(x) (((x) >> 19) & 0x1)
#define C_028804_INTERPOLATE_SRC_Z 0xFFF7FFFF
#define S_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((unsigned)(x) & 0x1) << 20)
#define G_028804_STATIC_ANCHOR_ASSOCIATIONS(x) (((x) >> 20) & 0x1)
#define C_028804_STATIC_ANCHOR_ASSOCIATIONS 0xFFEFFFFF
#define S_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((unsigned)(x) & 0x1) << 21)
#define G_028804_ALPHA_TO_MASK_EQAA_DISABLE(x) (((x) >> 21) & 0x1)
#define C_028804_ALPHA_TO_MASK_EQAA_DISABLE 0xFFDFFFFF
#define S_028804_OVERRASTERIZATION_AMOUNT(x) (((unsigned)(x) & 0x07) << 24)
#define G_028804_OVERRASTERIZATION_AMOUNT(x) (((x) >> 24) & 0x07)
#define C_028804_OVERRASTERIZATION_AMOUNT 0xF8FFFFFF
#define S_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((unsigned)(x) & 0x1) << 27)
#define G_028804_ENABLE_POSTZ_OVERRASTERIZATION(x) (((x) >> 27) & 0x1)
#define C_028804_ENABLE_POSTZ_OVERRASTERIZATION 0xF7FFFFFF
#define CM_R_028BDC_PA_SC_LINE_CNTL 0x28bdc
#define S_028BDC_EXPAND_LINE_WIDTH(x) (((unsigned)(x) & 0x1) << 9)
#define G_028BDC_EXPAND_LINE_WIDTH(x) (((x) >> 9) & 0x1)
#define C_028BDC_EXPAND_LINE_WIDTH 0xFFFFFDFF
#define S_028BDC_LAST_PIXEL(x) (((unsigned)(x) & 0x1) << 10)
#define G_028BDC_LAST_PIXEL(x) (((x) >> 10) & 0x1)
#define C_028BDC_LAST_PIXEL 0xFFFFFBFF
#define S_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((unsigned)(x) & 0x1) << 11)
#define G_028BDC_PERPENDICULAR_ENDCAP_ENA(x) (((x) >> 11) & 0x1)
#define C_028BDC_PERPENDICULAR_ENDCAP_ENA 0xFFFFF7FF
#define S_028BDC_DX10_DIAMOND_TEST_ENA(x) (((unsigned)(x) & 0x1) << 12)
#define G_028BDC_DX10_DIAMOND_TEST_ENA(x) (((x) >> 12) & 0x1)
#define C_028BDC_DX10_DIAMOND_TEST_ENA 0xFFFFEFFF
#define CM_R_028BE0_PA_SC_AA_CONFIG 0x28be0
#define S_028BE0_MSAA_NUM_SAMPLES(x) (((unsigned)(x) & 0x07) << 0)
#define G_028BE0_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x07)
#define C_028BE0_MSAA_NUM_SAMPLES 0xFFFFFFF8
#define S_028BE0_AA_MASK_CENTROID_DTMN(x) (((unsigned)(x) & 0x1) << 4)
#define G_028BE0_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1)
#define C_028BE0_AA_MASK_CENTROID_DTMN 0xFFFFFFEF
#define S_028BE0_MAX_SAMPLE_DIST(x) (((unsigned)(x) & 0x0F) << 13)
#define G_028BE0_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0x0F)
#define C_028BE0_MAX_SAMPLE_DIST 0xFFFE1FFF
#define S_028BE0_MSAA_EXPOSED_SAMPLES(x) (((unsigned)(x) & 0x07) << 20)
#define G_028BE0_MSAA_EXPOSED_SAMPLES(x) (((x) >> 20) & 0x07)
#define C_028BE0_MSAA_EXPOSED_SAMPLES 0xFF8FFFFF
#define S_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((unsigned)(x) & 0x03) << 24)
#define G_028BE0_DETAIL_TO_EXPOSED_MODE(x) (((x) >> 24) & 0x03)
#define C_028BE0_DETAIL_TO_EXPOSED_MODE 0xFCFFFFFF
#define CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 0x28bf8
#define CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0 0x28c08
#define CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0 0x28c18
#define CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0 0x28c28
#define R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x008960 /* read-only */ #define R_008960_VGT_STRMOUT_BUFFER_FILLED_SIZE_0 0x008960 /* read-only */
#define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x008964 /* read-only */ #define R_008964_VGT_STRMOUT_BUFFER_FILLED_SIZE_1 0x008964 /* read-only */
#define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x008968 /* read-only */ #define R_008968_VGT_STRMOUT_BUFFER_FILLED_SIZE_2 0x008968 /* read-only */
......
...@@ -28,6 +28,11 @@ ...@@ -28,6 +28,11 @@
#include "r600_cs.h" #include "r600_cs.h"
#include "util/u_memory.h" #include "util/u_memory.h"
#include "evergreend.h"
#define R_008490_CP_STRMOUT_CNTL 0x008490
#define R_028AB0_VGT_STRMOUT_EN 0x028AB0
#define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20
static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable); static void r600_set_streamout_enable(struct r600_common_context *rctx, bool enable);
...@@ -157,9 +162,7 @@ static void r600_flush_vgt_streamout(struct r600_common_context *rctx) ...@@ -157,9 +162,7 @@ static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
unsigned reg_strmout_cntl; unsigned reg_strmout_cntl;
/* The register is at different places on different ASICs. */ /* The register is at different places on different ASICs. */
if (rctx->chip_class >= CIK) { if (rctx->chip_class >= EVERGREEN) {
reg_strmout_cntl = R_0300FC_CP_STRMOUT_CNTL;
} else if (rctx->chip_class >= EVERGREEN) {
reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL; reg_strmout_cntl = R_0084FC_CP_STRMOUT_CNTL;
} else { } else {
reg_strmout_cntl = R_008490_CP_STRMOUT_CNTL; reg_strmout_cntl = R_008490_CP_STRMOUT_CNTL;
...@@ -178,8 +181,8 @@ static void r600_flush_vgt_streamout(struct r600_common_context *rctx) ...@@ -178,8 +181,8 @@ static void r600_flush_vgt_streamout(struct r600_common_context *rctx)
radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */ radeon_emit(cs, WAIT_REG_MEM_EQUAL); /* wait until the register is equal to the reference value */
radeon_emit(cs, reg_strmout_cntl >> 2); /* register */ radeon_emit(cs, reg_strmout_cntl >> 2); /* register */
radeon_emit(cs, 0); radeon_emit(cs, 0);
radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* reference value */ radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* reference value */
radeon_emit(cs, S_008490_OFFSET_UPDATE_DONE(1)); /* mask */ radeon_emit(cs, S_0084FC_OFFSET_UPDATE_DONE(1)); /* mask */
radeon_emit(cs, 4); /* poll interval */ radeon_emit(cs, 4); /* poll interval */
} }
...@@ -326,7 +329,6 @@ static void r600_emit_streamout_enable(struct r600_common_context *rctx, ...@@ -326,7 +329,6 @@ static void r600_emit_streamout_enable(struct r600_common_context *rctx,
strmout_config_reg = R_028B94_VGT_STRMOUT_CONFIG; strmout_config_reg = R_028B94_VGT_STRMOUT_CONFIG;
strmout_config_val |= strmout_config_val |=
S_028B94_RAST_STREAM(0) |
S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) | S_028B94_STREAMOUT_1_EN(r600_get_strmout_en(rctx)) |
S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) | S_028B94_STREAMOUT_2_EN(r600_get_strmout_en(rctx)) |
S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx)); S_028B94_STREAMOUT_3_EN(r600_get_strmout_en(rctx));
......
...@@ -25,6 +25,29 @@ ...@@ -25,6 +25,29 @@
#include "util/u_viewport.h" #include "util/u_viewport.h"
#include "tgsi/tgsi_scan.h" #include "tgsi/tgsi_scan.h"
#define R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ 0x028C0C
#define CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ 0x28be8
#define R_02843C_PA_CL_VPORT_XSCALE 0x02843C
#define R_028250_PA_SC_VPORT_SCISSOR_0_TL 0x028250
#define S_028250_TL_X(x) (((unsigned)(x) & 0x7FFF) << 0)
#define G_028250_TL_X(x) (((x) >> 0) & 0x7FFF)
#define C_028250_TL_X 0xFFFF8000
#define S_028250_TL_Y(x) (((unsigned)(x) & 0x7FFF) << 16)
#define G_028250_TL_Y(x) (((x) >> 16) & 0x7FFF)
#define C_028250_TL_Y 0x8000FFFF
#define S_028250_WINDOW_OFFSET_DISABLE(x) (((unsigned)(x) & 0x1) << 31)
#define G_028250_WINDOW_OFFSET_DISABLE(x) (((x) >> 31) & 0x1)
#define C_028250_WINDOW_OFFSET_DISABLE 0x7FFFFFFF
#define S_028254_BR_X(x) (((unsigned)(x) & 0x7FFF) << 0)
#define G_028254_BR_X(x) (((x) >> 0) & 0x7FFF)
#define C_028254_BR_X 0xFFFF8000
#define S_028254_BR_Y(x) (((unsigned)(x) & 0x7FFF) << 16)
#define G_028254_BR_Y(x) (((x) >> 16) & 0x7FFF)
#define C_028254_BR_Y 0x8000FFFF
#define R_0282D0_PA_SC_VPORT_ZMIN_0 0x0282D0
#define R_0282D4_PA_SC_VPORT_ZMAX_0 0x0282D4
#define GET_MAX_SCISSOR(rctx) (rctx->chip_class >= EVERGREEN ? 16384 : 8192) #define GET_MAX_SCISSOR(rctx) (rctx->chip_class >= EVERGREEN ? 16384 : 8192)
static void r600_set_scissor_states(struct pipe_context *ctx, static void r600_set_scissor_states(struct pipe_context *ctx,
......
...@@ -31,7 +31,7 @@ ...@@ -31,7 +31,7 @@
#define R600_CS_H #define R600_CS_H
#include "r600_pipe_common.h" #include "r600_pipe_common.h"
#include "amd/common/r600d_common.h" #include "amd/common/sid.h"
/** /**
* Return true if there is enough memory in VRAM and GTT for the buffers * Return true if there is enough memory in VRAM and GTT for the buffers
...@@ -115,10 +115,10 @@ radeon_add_to_buffer_list_check_mem(struct r600_common_context *rctx, ...@@ -115,10 +115,10 @@ radeon_add_to_buffer_list_check_mem(struct r600_common_context *rctx,
static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) static inline void radeon_set_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{ {
assert(reg < R600_CONTEXT_REG_OFFSET); assert(reg < SI_CONTEXT_REG_OFFSET);
assert(cs->current.cdw + 2 + num <= cs->current.max_dw); assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0)); radeon_emit(cs, PKT3(PKT3_SET_CONFIG_REG, num, 0));
radeon_emit(cs, (reg - R600_CONFIG_REG_OFFSET) >> 2); radeon_emit(cs, (reg - SI_CONFIG_REG_OFFSET) >> 2);
} }
static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
...@@ -129,10 +129,10 @@ static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned r ...@@ -129,10 +129,10 @@ static inline void radeon_set_config_reg(struct radeon_winsys_cs *cs, unsigned r
static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) static inline void radeon_set_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
{ {
assert(reg >= R600_CONTEXT_REG_OFFSET); assert(reg >= SI_CONTEXT_REG_OFFSET);
assert(cs->current.cdw + 2 + num <= cs->current.max_dw); assert(cs->current.cdw + 2 + num <= cs->current.max_dw);
radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0)); radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, num, 0));
radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2); radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2);
} }
static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
...@@ -145,10 +145,10 @@ static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs, ...@@ -145,10 +145,10 @@ static inline void radeon_set_context_reg_idx(struct radeon_winsys_cs *cs,
unsigned reg, unsigned idx, unsigned reg, unsigned idx,
unsigned value) unsigned value)
{ {
assert(reg >= R600_CONTEXT_REG_OFFSET); assert(reg >= SI_CONTEXT_REG_OFFSET);
assert(cs->current.cdw + 3 <= cs->current.max_dw); assert(cs->current.cdw + 3 <= cs->current.max_dw);
radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0)); radeon_emit(cs, PKT3(PKT3_SET_CONTEXT_REG, 1, 0));
radeon_emit(cs, (reg - R600_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28));
radeon_emit(cs, value); radeon_emit(cs, value);
} }
......
...@@ -28,7 +28,7 @@ ...@@ -28,7 +28,7 @@
#include "util/u_memory.h" #include "util/u_memory.h"
#include "r600_query.h" #include "r600_query.h"
#include "r600_pipe_common.h" #include "r600_pipe_common.h"
#include "amd/common/r600d_common.h" #include "amd/common/sid.h"
/* Max counters per HW block */ /* Max counters per HW block */
#define R600_QUERY_MAX_COUNTERS 16 #define R600_QUERY_MAX_COUNTERS 16
......
...@@ -36,6 +36,7 @@ ...@@ -36,6 +36,7 @@
#include "vl/vl_decoder.h" #include "vl/vl_decoder.h"
#include "vl/vl_video_buffer.h" #include "vl/vl_video_buffer.h"
#include "radeon/radeon_video.h" #include "radeon/radeon_video.h"
#include "amd/common/sid.h"
#include <inttypes.h> #include <inttypes.h>
#include <sys/utsname.h> #include <sys/utsname.h>
......
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#include "util/u_upload_mgr.h" #include "util/u_upload_mgr.h"
#include "os/os_time.h" #include "os/os_time.h"
#include "tgsi/tgsi_text.h" #include "tgsi/tgsi_text.h"
#include "amd/common/sid.h"
/* TODO: remove this: */ /* TODO: remove this: */
void si_update_prims_generated_query_state(struct r600_common_context *rctx, void si_update_prims_generated_query_state(struct r600_common_context *rctx,
...@@ -727,10 +728,10 @@ static unsigned event_type_for_stream(unsigned stream) ...@@ -727,10 +728,10 @@ static unsigned event_type_for_stream(unsigned stream)
{ {
switch (stream) { switch (stream) {
default: default:
case 0: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS; case 0: return V_028A90_SAMPLE_STREAMOUTSTATS;
case 1: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS1; case 1: return V_028A90_SAMPLE_STREAMOUTSTATS1;
case 2: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS2; case 2: return V_028A90_SAMPLE_STREAMOUTSTATS2;
case 3: return EVENT_TYPE_SAMPLE_STREAMOUTSTATS3; case 3: return V_028A90_SAMPLE_STREAMOUTSTATS3;
} }
} }
...@@ -755,7 +756,7 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx, ...@@ -755,7 +756,7 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
case PIPE_QUERY_OCCLUSION_PREDICATE: case PIPE_QUERY_OCCLUSION_PREDICATE:
case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1)); radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
radeon_emit(cs, va); radeon_emit(cs, va);
radeon_emit(cs, va >> 32); radeon_emit(cs, va >> 32);
break; break;
...@@ -784,7 +785,7 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx, ...@@ -784,7 +785,7 @@ static void r600_query_hw_do_emit_start(struct r600_common_context *ctx,
break; break;
case PIPE_QUERY_PIPELINE_STATISTICS: case PIPE_QUERY_PIPELINE_STATISTICS:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2)); radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
radeon_emit(cs, va); radeon_emit(cs, va);
radeon_emit(cs, va >> 32); radeon_emit(cs, va >> 32);
break; break;
...@@ -842,7 +843,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx, ...@@ -842,7 +843,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
va += 8; va += 8;
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) | EVENT_INDEX(1)); radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
radeon_emit(cs, va); radeon_emit(cs, va);
radeon_emit(cs, va >> 32); radeon_emit(cs, va >> 32);
...@@ -864,7 +865,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx, ...@@ -864,7 +865,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
va += 8; va += 8;
/* fall through */ /* fall through */
case PIPE_QUERY_TIMESTAMP: case PIPE_QUERY_TIMESTAMP:
si_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, si_gfx_write_event_eop(ctx, V_028A90_BOTTOM_OF_PIPE_TS,
0, EOP_DATA_SEL_TIMESTAMP, NULL, va, 0, EOP_DATA_SEL_TIMESTAMP, NULL, va,
0, query->b.type); 0, query->b.type);
fence_va = va + 8; fence_va = va + 8;
...@@ -874,7 +875,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx, ...@@ -874,7 +875,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
va += sample_size; va += sample_size;
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2)); radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
radeon_emit(cs, va); radeon_emit(cs, va);
radeon_emit(cs, va >> 32); radeon_emit(cs, va >> 32);
...@@ -888,7 +889,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx, ...@@ -888,7 +889,7 @@ static void r600_query_hw_do_emit_stop(struct r600_common_context *ctx,
RADEON_PRIO_QUERY); RADEON_PRIO_QUERY);
if (fence_va) if (fence_va)
si_gfx_write_event_eop(ctx, EVENT_TYPE_BOTTOM_OF_PIPE_TS, 0, si_gfx_write_event_eop(ctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
EOP_DATA_SEL_VALUE_32BIT, EOP_DATA_SEL_VALUE_32BIT,
query->buffer.buf, fence_va, 0x80000000, query->buffer.buf, fence_va, 0x80000000,
query->b.type); query->b.type);
......
...@@ -36,6 +36,7 @@ ...@@ -36,6 +36,7 @@
#include <errno.h> #include <errno.h>
#include <inttypes.h> #include <inttypes.h>
#include "state_tracker/drm_driver.h" #include "state_tracker/drm_driver.h"
#include "amd/common/sid.h"
static void r600_texture_discard_cmask(struct r600_common_screen *rscreen, static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
struct r600_texture *rtex); struct r600_texture *rtex);
...@@ -408,7 +409,7 @@ static void r600_texture_discard_cmask(struct r600_common_screen *rscreen, ...@@ -408,7 +409,7 @@ static void r600_texture_discard_cmask(struct r600_common_screen *rscreen,
rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8; rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8;
rtex->dirty_level_mask = 0; rtex->dirty_level_mask = 0;
rtex->cb_color_info &= ~SI_S_028C70_FAST_CLEAR(1); rtex->cb_color_info &= ~S_028C70_FAST_CLEAR(1);
if (rtex->cmask_buffer != &rtex->resource) if (rtex->cmask_buffer != &rtex->resource)
r600_resource_reference(&rtex->cmask_buffer, NULL); r600_resource_reference(&rtex->cmask_buffer, NULL);
...@@ -849,7 +850,7 @@ static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen, ...@@ -849,7 +850,7 @@ static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment); rtex->cmask.offset = align64(rtex->size, rtex->cmask.alignment);
rtex->size = rtex->cmask.offset + rtex->cmask.size; rtex->size = rtex->cmask.offset + rtex->cmask.size;
rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1); rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
} }
static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen, static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen,
...@@ -876,7 +877,7 @@ static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen ...@@ -876,7 +877,7 @@ static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen
/* update colorbuffer state bits */ /* update colorbuffer state bits */
rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8; rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
rtex->cb_color_info |= SI_S_028C70_FAST_CLEAR(1); rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
p_atomic_inc(&rscreen->compressed_colortex_counter); p_atomic_inc(&rscreen->compressed_colortex_counter);
} }
...@@ -2062,7 +2063,7 @@ unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap) ...@@ -2062,7 +2063,7 @@ unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap)
#define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz) #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */ if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
return V_0280A0_SWAP_STD; return V_028C70_SWAP_STD;
if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
return ~0U; return ~0U;
...@@ -2070,45 +2071,45 @@ unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap) ...@@ -2070,45 +2071,45 @@ unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap)
switch (desc->nr_channels) {