Commit 0ecf9b90 authored by Marek Olšák's avatar Marek Olšák

radeonsi: import cayman_msaa.c from drivers/radeon

Reviewed-by: default avatarNicolai Hähnle <nicolai.haehnle@amd.com>
parent 345f04ed
C_SOURCES := \
cayman_msaa.c \
r600_buffer_common.c \
r600_cs.h \
r600_gpu_load.c \
......
......@@ -638,7 +638,6 @@ bool si_common_context_init(struct r600_common_context *rctx,
si_init_context_texture_functions(rctx);
si_init_query_functions(rctx);
si_init_msaa(&rctx->b);
if (rctx->chip_class == CIK ||
rctx->chip_class == VI ||
......
......@@ -578,15 +578,6 @@ struct r600_common_context {
bool render_cond_invert;
bool render_cond_force_off; /* for u_blitter */
/* MSAA sample locations.
* The first index is the sample index.
* The second index is the coordinate: X, Y. */
float sample_locations_1x[1][2];
float sample_locations_2x[2][2];
float sample_locations_4x[4][2];
float sample_locations_8x[8][2];
float sample_locations_16x[16][2];
/* Statistics gathering for the DCC enablement heuristic. It can't be
* in r600_texture because r600_texture can be shared by multiple
* contexts. This is for back buffers only. We shouldn't get too many
......@@ -806,15 +797,6 @@ bool si_texture_disable_dcc(struct r600_common_context *rctx,
void si_init_screen_texture_functions(struct r600_common_screen *rscreen);
void si_init_context_texture_functions(struct r600_common_context *rctx);
/* cayman_msaa.c */
void si_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
unsigned sample_index, float *out_value);
void si_init_msaa(struct pipe_context *ctx);
void si_common_emit_msaa_sample_locs(struct radeon_winsys_cs *cs, int nr_samples);
void si_common_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
int ps_iter_samples, int overrast_samples,
unsigned sc_mode_cntl_1);
/* Inline helpers. */
......@@ -923,13 +905,6 @@ vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
#define R600_ERR(fmt, args...) \
fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
/* For MSAA sample positions. */
#define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
(((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
(((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
(((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
(((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
static inline int S_FIXED(float value, unsigned frac_bits)
{
return value * (1 << frac_bits);
......
......@@ -29,6 +29,7 @@ C_SOURCES := \
si_state.c \
si_state_binning.c \
si_state_draw.c \
si_state_msaa.c \
si_state_shaders.c \
si_state_streamout.c \
si_state_viewport.c \
......
......@@ -205,6 +205,7 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
si_init_compute_functions(sctx);
si_init_cp_dma_functions(sctx);
si_init_debug_functions(sctx);
si_init_msaa_functions(sctx);
si_init_streamout_functions(sctx);
if (sscreen->b.info.has_hw_decode) {
......
......@@ -543,6 +543,15 @@ struct si_context {
/* Bindless state */
bool uses_bindless_samplers;
bool uses_bindless_images;
/* MSAA sample locations.
* The first index is the sample index.
* The second index is the coordinate: X, Y. */
float sample_locations_1x[1][2];
float sample_locations_2x[2][2];
float sample_locations_4x[4][2];
float sample_locations_8x[8][2];
float sample_locations_16x[16][2];
};
/* cik_sdma.c */
......
......@@ -2886,19 +2886,19 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
/* Set sample locations as fragment shader constants. */
switch (sctx->framebuffer.nr_samples) {
case 1:
constbuf.user_buffer = sctx->b.sample_locations_1x;
constbuf.user_buffer = sctx->sample_locations_1x;
break;
case 2:
constbuf.user_buffer = sctx->b.sample_locations_2x;
constbuf.user_buffer = sctx->sample_locations_2x;
break;
case 4:
constbuf.user_buffer = sctx->b.sample_locations_4x;
constbuf.user_buffer = sctx->sample_locations_4x;
break;
case 8:
constbuf.user_buffer = sctx->b.sample_locations_8x;
constbuf.user_buffer = sctx->sample_locations_8x;
break;
case 16:
constbuf.user_buffer = sctx->b.sample_locations_16x;
constbuf.user_buffer = sctx->sample_locations_16x;
break;
default:
R600_ERR("Requested an invalid number of samples %i.\n",
......@@ -3191,7 +3191,7 @@ static void si_emit_msaa_sample_locs(struct si_context *sctx,
if (nr_samples != sctx->msaa_sample_locs.nr_samples) {
sctx->msaa_sample_locs.nr_samples = nr_samples;
si_common_emit_msaa_sample_locs(cs, nr_samples);
si_emit_sample_locations(cs, nr_samples);
}
if (sctx->b.family >= CHIP_POLARIS10) {
......@@ -3303,10 +3303,68 @@ static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
S_028A4C_FORCE_EOV_REZ_ENABLE(1);
si_common_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
sctx->ps_iter_samples,
sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
sc_mode_cntl_1);
int setup_samples = sctx->framebuffer.nr_samples > 1 ? sctx->framebuffer.nr_samples :
sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0;
/* Required by OpenGL line rasterization.
*
* TODO: We should also enable perpendicular endcaps for AA lines,
* but that requires implementing line stippling in the pixel
* shader. SC can only do line stippling with axis-aligned
* endcaps.
*/
unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
if (setup_samples > 1) {
/* distance from the pixel center, indexed by log2(nr_samples) */
static unsigned max_dist[] = {
0, /* unused */
4, /* 2x MSAA */
6, /* 4x MSAA */
7, /* 8x MSAA */
8, /* 16x MSAA */
};
unsigned log_samples = util_logbase2(setup_samples);
unsigned log_ps_iter_samples =
util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, sc_line_cntl |
S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
if (sctx->framebuffer.nr_samples > 1) {
radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
EG_S_028A4C_PS_ITER_SAMPLE(sctx->ps_iter_samples > 1) |
sc_mode_cntl_1);
} else if (sctx->smoothing_enabled) {
radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
sc_mode_cntl_1);
}
} else {
radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
sc_mode_cntl_1);
}
/* GFX9: Flush DFSM when the AA mode changes. */
if (sctx->screen->dfsm_allowed) {
......@@ -4447,7 +4505,6 @@ void si_init_state_functions(struct si_context *sctx)
sctx->b.b.set_stencil_ref = si_set_stencil_ref;
sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
sctx->b.b.get_sample_position = si_get_sample_position;
sctx->b.b.create_sampler_state = si_create_sampler_state;
sctx->b.b.delete_sampler_state = si_delete_sampler_state;
......
......@@ -423,6 +423,10 @@ void si_draw_rectangle(struct blitter_context *blitter,
const union blitter_attrib *attrib);
void si_trace_emit(struct si_context *sctx);
/* si_state_msaa.c */
void si_init_msaa_functions(struct si_context *sctx);
void si_emit_sample_locations(struct radeon_winsys_cs *cs, int nr_samples);
/* si_state_streamout.c */
void si_streamout_buffers_dirty(struct si_context *sctx);
void si_emit_streamout_end(struct si_context *sctx);
......
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