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In the same spirit as commit a5889d70 "i965/icl: Disable binding table prefetching". Fixes some 110+ intermittent piglit failures with tex-miplevel-selection variants. WA_1606682166: Incorrect TDL's SSP address shift in SARB for 16:6 & 18:8 modes. Disable the Sampler state prefetch functionality in the SARB by programming 0xB000[30] to '1'. This is to be done at boot time and the feature must remain disabled permanently. Anuj: Set SamplerCount = 0 for vs, gs, hs, ds and wm units as well. Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com> Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com> Cc: Mark Janes <mark.a.janes@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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