Commit 077d01b6 authored by Eric Anholt's avatar Eric Anholt

i965: Add support for instruction compaction.

This reduces program size by using some smaller encodings for common bit
patterns in the Gen ISA, with the hope of making programs fit in the
instruction cache better.

v2: Use larger bitshifts for the uncompressed field setups, in line with the
    way it's described in the spec.  Consistently name a brw_compile "p" like
    all other code.  Add a couple more tests.  Consistently call things
    "compacted" not "compressed" (which is a different feature).  Drop the
    explicit check for not compacting SENDs, which is unjustified and already
    implied by our lack of support for immediate values.
Reviewed-by: Paul Berry's avatarPaul Berry <stereotype441@gmail.com>
parent f5e27063
Makefile
i965_symbols_test
libi965_dri.la
test_eu_compact
......@@ -51,16 +51,30 @@ libi965_dri_la_SOURCES = \
$(i965_C_FILES) \
$(i965_CXX_FILES)
# list of libs to be linked against by i965_dri.so and i965 test programs.
COMMON_LIBS = \
libi965_dri.la \
$(DRI_LIB_DEPS) \
$(INTEL_LIBS) \
../common/libdricommon.la
TEST_LIBS = \
$(COMMON_LIBS) \
-lrt \
../common/libdri_test_stubs.la
i965_dri_la_SOURCES =
i965_dri_la_LIBADD = $(COMMON_LIBS)
i965_dri_la_LDFLAGS = -module -avoid-version -shared
TESTS = test_eu_compact
check_PROGRAMS = test_eu_compact
test_eu_compact_SOURCES = \
test_eu_compact.c
nodist_EXTRA_test_eu_compact_SOURCES = dummy.cpp
test_eu_compact_LDADD = $(TEST_LIBS)
# Provide compatibility with scripts for the old Mesa build system for
# a while by putting a link to the driver into /lib of the build tree.
all-local: i965_dri.la
......
......@@ -44,6 +44,7 @@ i965_C_FILES = \
brw_draw.c \
brw_draw_upload.c \
brw_eu.c \
brw_eu_compact.c \
brw_eu_debug.c \
brw_eu_emit.c \
brw_eu_util.c \
......
......@@ -214,6 +214,11 @@ const GLuint *brw_get_program( struct brw_compile *p,
{
GLuint i;
brw_compact_instructions(p);
/* We emit a cacheline (8 instructions) of NOPs at the end of the program to
* make sure that instruction prefetch doesn't wander off into some other BO.
*/
for (i = 0; i < 8; i++)
brw_NOP(p);
......@@ -224,19 +229,36 @@ const GLuint *brw_get_program( struct brw_compile *p,
void
brw_dump_compile(struct brw_compile *p, FILE *out, int start, int end)
{
struct brw_context *brw = p->brw;
struct intel_context *intel = &brw->intel;
void *store = p->store;
bool dump_hex = false;
for (int offset = start; offset < end; offset += 16) {
for (int offset = start; offset < end;) {
struct brw_instruction *insn = store + offset;
struct brw_instruction uncompacted;
printf("0x%08x: ", offset);
if (0) {
printf("0x%08x 0x%08x 0x%08x 0x%08x ",
((uint32_t *)insn)[3],
((uint32_t *)insn)[2],
((uint32_t *)insn)[1],
((uint32_t *)insn)[0]);
if (insn->header.cmpt_control) {
struct brw_compact_instruction *compacted = (void *)insn;
if (dump_hex) {
printf("0x%08x 0x%08x ",
((uint32_t *)insn)[1],
((uint32_t *)insn)[0]);
}
brw_uncompact_instruction(intel, &uncompacted, compacted);
insn = &uncompacted;
offset += 8;
} else {
if (dump_hex) {
printf("0x%08x 0x%08x 0x%08x 0x%08x ",
((uint32_t *)insn)[3],
((uint32_t *)insn)[2],
((uint32_t *)insn)[1],
((uint32_t *)insn)[0]);
}
offset += 16;
}
brw_disasm(stdout, insn, p->brw->intel.gen);
......
......@@ -1107,6 +1107,19 @@ void brw_set_uip_jip(struct brw_compile *p);
uint32_t brw_swap_cmod(uint32_t cmod);
/* brw_eu_compact.c */
void brw_compact_instructions(struct brw_compile *p);
void brw_uncompact_instruction(struct intel_context *intel,
struct brw_instruction *dst,
struct brw_compact_instruction *src);
bool brw_try_compact_instruction(struct brw_compile *p,
struct brw_compact_instruction *dst,
struct brw_instruction *src);
void brw_debug_compact_uncompact(struct intel_context *intel,
struct brw_instruction *orig,
struct brw_instruction *uncompacted);
/* brw_optimize.c */
void brw_optimize(struct brw_compile *p);
void brw_remove_duplicate_mrf_moves(struct brw_compile *p);
......
This diff is collapsed.
......@@ -32,6 +32,7 @@
#include "main/mtypes.h"
#include "main/imports.h"
#include "brw_context.h"
#include "brw_eu.h"
void brw_print_reg( struct brw_reg hwreg )
......
......@@ -1947,6 +1947,12 @@ fs_visitor::run()
brw_wm_payload_setup(brw, c);
if (c->dispatch_width == 16) {
/* We have to do a compaction pass now, or the one at the end of
* execution will squash down where our prog_offset start needs
* to be.
*/
brw_compact_instructions(p);
/* align to 64 byte boundary. */
while ((c->func.nr_insn * sizeof(struct brw_instruction)) % 64) {
brw_NOP(p);
......
......@@ -1048,6 +1048,8 @@ struct brw_instruction
GLuint dest_subreg_nr:3;
GLuint dest_reg_nr:8;
} da3src;
uint32_t ud;
} bits1;
......@@ -1137,6 +1139,8 @@ struct brw_instruction
GLuint src1_swizzle:8;
GLuint src1_subreg_nr_low:2;
} da3src;
uint32_t ud;
} bits2;
union
......@@ -1534,5 +1538,27 @@ struct brw_instruction
} bits3;
};
struct brw_compact_instruction {
struct {
unsigned opcode:7; /* 0- 6 */
unsigned debug_control:1; /* 7- 7 */
unsigned control_index:5; /* 8-12 */
unsigned data_type_index:5; /* 13-17 */
unsigned sub_reg_index:5; /* 18-22 */
unsigned acc_wr_control:1; /* 23-23 */
unsigned conditionalmod:4; /* 24-27 */
unsigned flag_reg_nr:1; /* 28-28 */
unsigned cmpt_ctrl:1; /* 29-29 */
unsigned src0_index:2; /* 30-31 */
} dw0;
struct {
unsigned src0_index:3; /* 32-24 */
unsigned src1_index:5; /* 35-39 */
unsigned dst_reg_nr:8; /* 40-47 */
unsigned src0_reg_nr:8; /* 48-55 */
unsigned src1_reg_nr:8; /* 56-63 */
} dw1;
};
#endif
/*
* Copyright © 2012 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*/
#include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include "glsl/ralloc.h"
#include "brw_context.h"
#include "brw_eu.h"
static bool
test_compact_instruction(struct brw_compile *p, struct brw_instruction src)
{
struct brw_context *brw = p->brw;
struct intel_context *intel = &brw->intel;
struct brw_compact_instruction dst;
memset(&dst, 0xd0, sizeof(dst));
if (brw_try_compact_instruction(p, &dst, &src)) {
struct brw_instruction uncompacted;
brw_uncompact_instruction(intel, &uncompacted, &dst);
if (memcmp(&uncompacted, &src, sizeof(src))) {
brw_debug_compact_uncompact(intel, &src, &uncompacted);
return false;
}
} else {
struct brw_compact_instruction unchanged;
memset(&unchanged, 0xd0, sizeof(unchanged));
/* It's not supposed to change dst unless it compacted. */
if (memcmp(&unchanged, &dst, sizeof(dst))) {
fprintf(stderr, "Failed to compact, but dst changed\n");
fprintf(stderr, " Instruction: ");
brw_disasm(stderr, &src, intel->gen);
return false;
}
}
return true;
}
/**
* When doing fuzz testing, pad bits won't round-trip.
*
* This sort of a superset of skip_bit, which is testing for changing bits that
* aren't worth testing for fuzzing. We also just want to clear bits that
* become meaningless once fuzzing twiddles a related bit.
*/
static void
clear_pad_bits(struct brw_instruction *inst)
{
if (inst->header.opcode != BRW_OPCODE_SEND &&
inst->header.opcode != BRW_OPCODE_SENDC &&
inst->header.opcode != BRW_OPCODE_BREAK &&
inst->header.opcode != BRW_OPCODE_CONTINUE &&
inst->bits1.da1.src0_reg_file != BRW_IMMEDIATE_VALUE &&
inst->bits1.da1.src1_reg_file != BRW_IMMEDIATE_VALUE) {
if (inst->bits3.da1.src1_address_mode)
inst->bits3.ia1.pad1 = 0;
else
inst->bits3.da1.pad0 = 0;
}
}
static bool
skip_bit(struct brw_instruction *src, int bit)
{
/* pad bit */
if (bit == 7)
return true;
/* The compact bit -- uncompacted can't have it set. */
if (bit == 29)
return true;
/* pad bit */
if (bit == 47)
return true;
/* pad bits */
if (bit >= 90 && bit <= 95)
return true;
/* sometimes these are pad bits. */
if (src->header.opcode != BRW_OPCODE_SEND &&
src->header.opcode != BRW_OPCODE_SENDC &&
src->header.opcode != BRW_OPCODE_BREAK &&
src->header.opcode != BRW_OPCODE_CONTINUE &&
src->bits1.da1.src0_reg_file != BRW_IMMEDIATE_VALUE &&
src->bits1.da1.src1_reg_file != BRW_IMMEDIATE_VALUE &&
bit >= 121) {
return true;
}
return false;
}
static bool
test_fuzz_compact_instruction(struct brw_compile *p,
struct brw_instruction src)
{
for (int bit0 = 0; bit0 < 128; bit0++) {
if (skip_bit(&src, bit0))
continue;
for (int bit1 = 0; bit1 < 128; bit1++) {
struct brw_instruction instr = src;
uint32_t *bits = (uint32_t *)&instr;
if (skip_bit(&src, bit1))
continue;
bits[bit0 / 32] ^= (1 << (bit0 & 31));
bits[bit1 / 32] ^= (1 << (bit1 & 31));
clear_pad_bits(&instr);
if (!test_compact_instruction(p, instr)) {
printf(" twiddled bits for fuzzing %d, %d\n", bit0, bit1);
return false;
}
}
}
return true;
}
static void
gen_ADD_GRF_GRF_GRF(struct brw_compile *p)
{
struct brw_reg g0 = brw_vec8_grf(0, 0);
struct brw_reg g2 = brw_vec8_grf(2, 0);
struct brw_reg g4 = brw_vec8_grf(4, 0);
brw_ADD(p, g0, g2, g4);
}
static void
gen_ADD_GRF_GRF_IMM(struct brw_compile *p)
{
struct brw_reg g0 = brw_vec8_grf(0, 0);
struct brw_reg g2 = brw_vec8_grf(2, 0);
brw_ADD(p, g0, g2, brw_imm_f(1.0));
}
static void
gen_ADD_GRF_GRF_IMM_d(struct brw_compile *p)
{
struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_D);
struct brw_reg g2 = retype(brw_vec8_grf(2, 0), BRW_REGISTER_TYPE_D);
brw_ADD(p, g0, g2, brw_imm_d(1));
}
static void
gen_MOV_GRF_GRF(struct brw_compile *p)
{
struct brw_reg g0 = brw_vec8_grf(0, 0);
struct brw_reg g2 = brw_vec8_grf(2, 0);
brw_MOV(p, g0, g2);
}
static void
gen_ADD_MRF_GRF_GRF(struct brw_compile *p)
{
struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0);
struct brw_reg g2 = brw_vec8_grf(2, 0);
struct brw_reg g4 = brw_vec8_grf(4, 0);
brw_ADD(p, m6, g2, g4);
}
static void
gen_ADD_vec1_GRF_GRF_GRF(struct brw_compile *p)
{
struct brw_reg g0 = brw_vec1_grf(0, 0);
struct brw_reg g2 = brw_vec1_grf(2, 0);
struct brw_reg g4 = brw_vec1_grf(4, 0);
brw_ADD(p, g0, g2, g4);
}
static void
gen_PLN_MRF_GRF_GRF(struct brw_compile *p)
{
struct brw_reg m6 = brw_vec8_reg(BRW_MESSAGE_REGISTER_FILE, 6, 0);
struct brw_reg interp = brw_vec1_grf(2, 0);
struct brw_reg g4 = brw_vec8_grf(4, 0);
brw_PLN(p, m6, interp, g4);
}
static void
gen_f0_MOV_GRF_GRF(struct brw_compile *p)
{
struct brw_reg g0 = brw_vec8_grf(0, 0);
struct brw_reg g2 = brw_vec8_grf(2, 0);
brw_push_insn_state(p);
brw_set_predicate_control(p, true);
brw_MOV(p, g0, g2);
brw_pop_insn_state(p);
}
/* The handling of f1 vs f0 changes between gen6 and gen7. Explicitly test
* it, so that we run the fuzzing can run over all the other bits that might
* interact with it.
*/
static void
gen_f1_MOV_GRF_GRF(struct brw_compile *p)
{
struct brw_reg g0 = brw_vec8_grf(0, 0);
struct brw_reg g2 = brw_vec8_grf(2, 0);
brw_push_insn_state(p);
brw_set_predicate_control(p, true);
current_insn(p)->bits2.da1.flag_reg_nr = 1;
brw_MOV(p, g0, g2);
brw_pop_insn_state(p);
}
struct {
void (*func)(struct brw_compile *p);
} tests[] = {
{ gen_MOV_GRF_GRF },
{ gen_ADD_GRF_GRF_GRF },
{ gen_ADD_GRF_GRF_IMM },
{ gen_ADD_GRF_GRF_IMM_d },
{ gen_ADD_MRF_GRF_GRF },
{ gen_ADD_vec1_GRF_GRF_GRF },
{ gen_PLN_MRF_GRF_GRF },
{ gen_f0_MOV_GRF_GRF },
{ gen_f1_MOV_GRF_GRF },
};
int
main(int argc, char **argv)
{
struct brw_context *brw = calloc(1, sizeof(*brw));
struct intel_context *intel = &brw->intel;
intel->gen = 6;
int ret = 0;
for (int i = 0; i < ARRAY_SIZE(tests); i++) {
for (int align_16 = 0; align_16 <= 1; align_16++) {
struct brw_compile *p = rzalloc(NULL, struct brw_compile);
brw_init_compile(brw, p, p);
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
if (align_16)
brw_set_access_mode(p, BRW_ALIGN_16);
else
brw_set_access_mode(p, BRW_ALIGN_1);
tests[i].func(p);
assert(p->nr_insn == 1);
if (!test_compact_instruction(p, p->store[0])) {
ret = 1;
continue;
}
if (!test_fuzz_compact_instruction(p, p->store[0])) {
ret = 1;
continue;
}
ralloc_free(p);
}
}
return ret;
}
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment