a2xx.xml.h 108 KB
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#ifndef A2XX_XML
#define A2XX_XML

/* Autogenerated file, DO NOT EDIT manually!

This file was generated by the rules-ng-ng headergen tool in this git repository:
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http://github.com/freedreno/envytools/
git clone https://github.com/freedreno/envytools.git
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The rules-ng-ng source files this header was generated from are:
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- ./rnndb/adreno/a2xx.xml          (  79608 bytes, from 2018-12-21 03:07:09)
- ./rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-09-02 13:35:19)
- ./rnndb/adreno/adreno_common.xml (  14201 bytes, from 2018-09-07 18:12:21)
- ./rnndb/adreno/adreno_pm4.xml    (  42626 bytes, from 2018-09-17 18:20:14)
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Copyright (C) 2013-2018 by the following authors:
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- Rob Clark <robdclark@gmail.com> (robclark)
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- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
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Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:

The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/


enum a2xx_rb_dither_type {
	DITHER_PIXEL = 0,
	DITHER_SUBPIXEL = 1,
};

enum a2xx_colorformatx {
	COLORX_4_4_4_4 = 0,
	COLORX_1_5_5_5 = 1,
	COLORX_5_6_5 = 2,
	COLORX_8 = 3,
	COLORX_8_8 = 4,
	COLORX_8_8_8_8 = 5,
	COLORX_S8_8_8_8 = 6,
	COLORX_16_FLOAT = 7,
	COLORX_16_16_FLOAT = 8,
	COLORX_16_16_16_16_FLOAT = 9,
	COLORX_32_FLOAT = 10,
	COLORX_32_32_FLOAT = 11,
	COLORX_32_32_32_32_FLOAT = 12,
	COLORX_2_3_3 = 13,
	COLORX_8_8_8 = 14,
};

enum a2xx_sq_surfaceformat {
	FMT_1_REVERSE = 0,
	FMT_1 = 1,
	FMT_8 = 2,
	FMT_1_5_5_5 = 3,
	FMT_5_6_5 = 4,
	FMT_6_5_5 = 5,
	FMT_8_8_8_8 = 6,
	FMT_2_10_10_10 = 7,
	FMT_8_A = 8,
	FMT_8_B = 9,
	FMT_8_8 = 10,
	FMT_Cr_Y1_Cb_Y0 = 11,
	FMT_Y1_Cr_Y0_Cb = 12,
	FMT_5_5_5_1 = 13,
	FMT_8_8_8_8_A = 14,
	FMT_4_4_4_4 = 15,
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	FMT_8_8_8 = 16,
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	FMT_DXT1 = 18,
	FMT_DXT2_3 = 19,
	FMT_DXT4_5 = 20,
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	FMT_10_10_10_2 = 21,
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	FMT_24_8 = 22,
	FMT_16 = 24,
	FMT_16_16 = 25,
	FMT_16_16_16_16 = 26,
	FMT_16_EXPAND = 27,
	FMT_16_16_EXPAND = 28,
	FMT_16_16_16_16_EXPAND = 29,
	FMT_16_FLOAT = 30,
	FMT_16_16_FLOAT = 31,
	FMT_16_16_16_16_FLOAT = 32,
	FMT_32 = 33,
	FMT_32_32 = 34,
	FMT_32_32_32_32 = 35,
	FMT_32_FLOAT = 36,
	FMT_32_32_FLOAT = 37,
	FMT_32_32_32_32_FLOAT = 38,
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	FMT_ATI_TC_RGB = 39,
	FMT_ATI_TC_RGBA = 40,
	FMT_ATI_TC_555_565_RGB = 41,
	FMT_ATI_TC_555_565_RGBA = 42,
	FMT_ATI_TC_RGBA_INTERP = 43,
	FMT_ATI_TC_555_565_RGBA_INTERP = 44,
	FMT_ETC1_RGBA_INTERP = 46,
	FMT_ETC1_RGB = 47,
	FMT_ETC1_RGBA = 48,
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	FMT_DXN = 49,
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	FMT_2_3_3 = 51,
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	FMT_2_10_10_10_AS_16_16_16_16 = 54,
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	FMT_10_10_10_2_AS_16_16_16_16 = 55,
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	FMT_32_32_32_FLOAT = 57,
	FMT_DXT3A = 58,
	FMT_DXT5A = 59,
	FMT_CTX1 = 60,
};

enum a2xx_sq_ps_vtx_mode {
	POSITION_1_VECTOR = 0,
	POSITION_2_VECTORS_UNUSED = 1,
	POSITION_2_VECTORS_SPRITE = 2,
	POSITION_2_VECTORS_EDGE = 3,
	POSITION_2_VECTORS_KILL = 4,
	POSITION_2_VECTORS_SPRITE_KILL = 5,
	POSITION_2_VECTORS_EDGE_KILL = 6,
	MULTIPASS = 7,
};

enum a2xx_sq_sample_cntl {
	CENTROIDS_ONLY = 0,
	CENTERS_ONLY = 1,
	CENTROIDS_AND_CENTERS = 2,
};

enum a2xx_dx_clip_space {
	DXCLIP_OPENGL = 0,
	DXCLIP_DIRECTX = 1,
};

enum a2xx_pa_su_sc_polymode {
	POLY_DISABLED = 0,
	POLY_DUALMODE = 1,
};

enum a2xx_rb_edram_mode {
	EDRAM_NOP = 0,
	COLOR_DEPTH = 4,
	DEPTH_ONLY = 5,
	EDRAM_COPY = 6,
};

enum a2xx_pa_sc_pattern_bit_order {
	LITTLE = 0,
	BIG = 1,
};

enum a2xx_pa_sc_auto_reset_cntl {
	NEVER = 0,
	EACH_PRIMITIVE = 1,
	EACH_PACKET = 2,
};

enum a2xx_pa_pixcenter {
	PIXCENTER_D3D = 0,
	PIXCENTER_OGL = 1,
};

enum a2xx_pa_roundmode {
	TRUNCATE = 0,
	ROUND = 1,
	ROUNDTOEVEN = 2,
	ROUNDTOODD = 3,
};

enum a2xx_pa_quantmode {
	ONE_SIXTEENTH = 0,
	ONE_EIGTH = 1,
	ONE_QUARTER = 2,
	ONE_HALF = 3,
	ONE = 4,
};

enum a2xx_rb_copy_sample_select {
	SAMPLE_0 = 0,
	SAMPLE_1 = 1,
	SAMPLE_2 = 2,
	SAMPLE_3 = 3,
	SAMPLE_01 = 4,
	SAMPLE_23 = 5,
	SAMPLE_0123 = 6,
};

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enum a2xx_rb_blend_opcode {
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	BLEND2_DST_PLUS_SRC = 0,
	BLEND2_SRC_MINUS_DST = 1,
	BLEND2_MIN_DST_SRC = 2,
	BLEND2_MAX_DST_SRC = 3,
	BLEND2_DST_MINUS_SRC = 4,
	BLEND2_DST_PLUS_SRC_BIAS = 5,
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};

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enum a2xx_su_perfcnt_select {
	PERF_PAPC_PASX_REQ = 0,
	PERF_PAPC_PASX_FIRST_VECTOR = 2,
	PERF_PAPC_PASX_SECOND_VECTOR = 3,
	PERF_PAPC_PASX_FIRST_DEAD = 4,
	PERF_PAPC_PASX_SECOND_DEAD = 5,
	PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
	PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
	PERF_PAPC_PA_INPUT_PRIM = 8,
	PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
	PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
	PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
	PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
	PERF_PAPC_CLPR_CULL_PRIM = 13,
	PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
	PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
	PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
	PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
	PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
	PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
	PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
	PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
	PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
	PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
	PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
	PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
	PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
	PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
	PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
	PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
	PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
	PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
	PERF_PAPC_CLSM_NULL_PRIM = 36,
	PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
	PERF_PAPC_CLSM_CLIP_PRIM = 38,
	PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
	PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
	PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
	PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
	PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
	PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
	PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
	PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
	PERF_PAPC_SU_INPUT_PRIM = 47,
	PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
	PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
	PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
	PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
	PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
	PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
	PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
	PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
	PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
	PERF_PAPC_SU_OUTPUT_PRIM = 57,
	PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
	PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
	PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
	PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
	PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
	PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
	PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
	PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
	PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
	PERF_PAPC_PASX_REQ_IDLE = 69,
	PERF_PAPC_PASX_REQ_BUSY = 70,
	PERF_PAPC_PASX_REQ_STALLED = 71,
	PERF_PAPC_PASX_REC_IDLE = 72,
	PERF_PAPC_PASX_REC_BUSY = 73,
	PERF_PAPC_PASX_REC_STARVED_SX = 74,
	PERF_PAPC_PASX_REC_STALLED = 75,
	PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
	PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
	PERF_PAPC_CCGSM_IDLE = 78,
	PERF_PAPC_CCGSM_BUSY = 79,
	PERF_PAPC_CCGSM_STALLED = 80,
	PERF_PAPC_CLPRIM_IDLE = 81,
	PERF_PAPC_CLPRIM_BUSY = 82,
	PERF_PAPC_CLPRIM_STALLED = 83,
	PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
	PERF_PAPC_CLIPSM_IDLE = 85,
	PERF_PAPC_CLIPSM_BUSY = 86,
	PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
	PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
	PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
	PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
	PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
	PERF_PAPC_CLIPGA_IDLE = 92,
	PERF_PAPC_CLIPGA_BUSY = 93,
	PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
	PERF_PAPC_CLIPGA_STALLED = 95,
	PERF_PAPC_CLIP_IDLE = 96,
	PERF_PAPC_CLIP_BUSY = 97,
	PERF_PAPC_SU_IDLE = 98,
	PERF_PAPC_SU_BUSY = 99,
	PERF_PAPC_SU_STARVED_CLIP = 100,
	PERF_PAPC_SU_STALLED_SC = 101,
	PERF_PAPC_SU_FACENESS_CULL = 102,
};

enum a2xx_sc_perfcnt_select {
	SC_SR_WINDOW_VALID = 0,
	SC_CW_WINDOW_VALID = 1,
	SC_QM_WINDOW_VALID = 2,
	SC_FW_WINDOW_VALID = 3,
	SC_EZ_WINDOW_VALID = 4,
	SC_IT_WINDOW_VALID = 5,
	SC_STARVED_BY_PA = 6,
	SC_STALLED_BY_RB_TILE = 7,
	SC_STALLED_BY_RB_SAMP = 8,
	SC_STARVED_BY_RB_EZ = 9,
	SC_STALLED_BY_SAMPLE_FF = 10,
	SC_STALLED_BY_SQ = 11,
	SC_STALLED_BY_SP = 12,
	SC_TOTAL_NO_PRIMS = 13,
	SC_NON_EMPTY_PRIMS = 14,
	SC_NO_TILES_PASSING_QM = 15,
	SC_NO_PIXELS_PRE_EZ = 16,
	SC_NO_PIXELS_POST_EZ = 17,
};

enum a2xx_vgt_perfcount_select {
	VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
	VGT_SQ_SEND = 1,
	VGT_SQ_STALLED = 2,
	VGT_SQ_STARVED_BUSY = 3,
	VGT_SQ_STARVED_IDLE = 4,
	VGT_SQ_STATIC = 5,
	VGT_PA_EVENT_WINDOW_ACTIVE = 6,
	VGT_PA_CLIP_V_SEND = 7,
	VGT_PA_CLIP_V_STALLED = 8,
	VGT_PA_CLIP_V_STARVED_BUSY = 9,
	VGT_PA_CLIP_V_STARVED_IDLE = 10,
	VGT_PA_CLIP_V_STATIC = 11,
	VGT_PA_CLIP_P_SEND = 12,
	VGT_PA_CLIP_P_STALLED = 13,
	VGT_PA_CLIP_P_STARVED_BUSY = 14,
	VGT_PA_CLIP_P_STARVED_IDLE = 15,
	VGT_PA_CLIP_P_STATIC = 16,
	VGT_PA_CLIP_S_SEND = 17,
	VGT_PA_CLIP_S_STALLED = 18,
	VGT_PA_CLIP_S_STARVED_BUSY = 19,
	VGT_PA_CLIP_S_STARVED_IDLE = 20,
	VGT_PA_CLIP_S_STATIC = 21,
	RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
	RBIU_IMMED_DATA_FIFO_STARVED = 23,
	RBIU_IMMED_DATA_FIFO_STALLED = 24,
	RBIU_DMA_REQUEST_FIFO_STARVED = 25,
	RBIU_DMA_REQUEST_FIFO_STALLED = 26,
	RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
	RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
	BIN_PRIM_NEAR_CULL = 29,
	BIN_PRIM_ZERO_CULL = 30,
	BIN_PRIM_FAR_CULL = 31,
	BIN_PRIM_BIN_CULL = 32,
	BIN_PRIM_FACE_CULL = 33,
	SPARE34 = 34,
	SPARE35 = 35,
	SPARE36 = 36,
	SPARE37 = 37,
	SPARE38 = 38,
	SPARE39 = 39,
	TE_SU_IN_VALID = 40,
	TE_SU_IN_READ = 41,
	TE_SU_IN_PRIM = 42,
	TE_SU_IN_EOP = 43,
	TE_SU_IN_NULL_PRIM = 44,
	TE_WK_IN_VALID = 45,
	TE_WK_IN_READ = 46,
	TE_OUT_PRIM_VALID = 47,
	TE_OUT_PRIM_READ = 48,
};

enum a2xx_tcr_perfcount_select {
	DGMMPD_IPMUX0_STALL = 0,
	DGMMPD_IPMUX_ALL_STALL = 4,
	OPMUX0_L2_WRITES = 5,
};

enum a2xx_tp_perfcount_select {
	POINT_QUADS = 0,
	BILIN_QUADS = 1,
	ANISO_QUADS = 2,
	MIP_QUADS = 3,
	VOL_QUADS = 4,
	MIP_VOL_QUADS = 5,
	MIP_ANISO_QUADS = 6,
	VOL_ANISO_QUADS = 7,
	ANISO_2_1_QUADS = 8,
	ANISO_4_1_QUADS = 9,
	ANISO_6_1_QUADS = 10,
	ANISO_8_1_QUADS = 11,
	ANISO_10_1_QUADS = 12,
	ANISO_12_1_QUADS = 13,
	ANISO_14_1_QUADS = 14,
	ANISO_16_1_QUADS = 15,
	MIP_VOL_ANISO_QUADS = 16,
	ALIGN_2_QUADS = 17,
	ALIGN_4_QUADS = 18,
	PIX_0_QUAD = 19,
	PIX_1_QUAD = 20,
	PIX_2_QUAD = 21,
	PIX_3_QUAD = 22,
	PIX_4_QUAD = 23,
	TP_MIPMAP_LOD0 = 24,
	TP_MIPMAP_LOD1 = 25,
	TP_MIPMAP_LOD2 = 26,
	TP_MIPMAP_LOD3 = 27,
	TP_MIPMAP_LOD4 = 28,
	TP_MIPMAP_LOD5 = 29,
	TP_MIPMAP_LOD6 = 30,
	TP_MIPMAP_LOD7 = 31,
	TP_MIPMAP_LOD8 = 32,
	TP_MIPMAP_LOD9 = 33,
	TP_MIPMAP_LOD10 = 34,
	TP_MIPMAP_LOD11 = 35,
	TP_MIPMAP_LOD12 = 36,
	TP_MIPMAP_LOD13 = 37,
	TP_MIPMAP_LOD14 = 38,
};

enum a2xx_tcm_perfcount_select {
	QUAD0_RD_LAT_FIFO_EMPTY = 0,
	QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
	QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
	QUAD0_RD_LAT_FIFO_FULL = 5,
	QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
	READ_STARVED_QUAD0 = 28,
	READ_STARVED = 32,
	READ_STALLED_QUAD0 = 33,
	READ_STALLED = 37,
	VALID_READ_QUAD0 = 38,
	TC_TP_STARVED_QUAD0 = 42,
	TC_TP_STARVED = 46,
};

enum a2xx_tcf_perfcount_select {
	VALID_CYCLES = 0,
	SINGLE_PHASES = 1,
	ANISO_PHASES = 2,
	MIP_PHASES = 3,
	VOL_PHASES = 4,
	MIP_VOL_PHASES = 5,
	MIP_ANISO_PHASES = 6,
	VOL_ANISO_PHASES = 7,
	ANISO_2_1_PHASES = 8,
	ANISO_4_1_PHASES = 9,
	ANISO_6_1_PHASES = 10,
	ANISO_8_1_PHASES = 11,
	ANISO_10_1_PHASES = 12,
	ANISO_12_1_PHASES = 13,
	ANISO_14_1_PHASES = 14,
	ANISO_16_1_PHASES = 15,
	MIP_VOL_ANISO_PHASES = 16,
	ALIGN_2_PHASES = 17,
	ALIGN_4_PHASES = 18,
	TPC_BUSY = 19,
	TPC_STALLED = 20,
	TPC_STARVED = 21,
	TPC_WORKING = 22,
	TPC_WALKER_BUSY = 23,
	TPC_WALKER_STALLED = 24,
	TPC_WALKER_WORKING = 25,
	TPC_ALIGNER_BUSY = 26,
	TPC_ALIGNER_STALLED = 27,
	TPC_ALIGNER_STALLED_BY_BLEND = 28,
	TPC_ALIGNER_STALLED_BY_CACHE = 29,
	TPC_ALIGNER_WORKING = 30,
	TPC_BLEND_BUSY = 31,
	TPC_BLEND_SYNC = 32,
	TPC_BLEND_STARVED = 33,
	TPC_BLEND_WORKING = 34,
	OPCODE_0x00 = 35,
	OPCODE_0x01 = 36,
	OPCODE_0x04 = 37,
	OPCODE_0x10 = 38,
	OPCODE_0x11 = 39,
	OPCODE_0x12 = 40,
	OPCODE_0x13 = 41,
	OPCODE_0x18 = 42,
	OPCODE_0x19 = 43,
	OPCODE_0x1A = 44,
	OPCODE_OTHER = 45,
	IN_FIFO_0_EMPTY = 56,
	IN_FIFO_0_LT_HALF_FULL = 57,
	IN_FIFO_0_HALF_FULL = 58,
	IN_FIFO_0_FULL = 59,
	IN_FIFO_TPC_EMPTY = 72,
	IN_FIFO_TPC_LT_HALF_FULL = 73,
	IN_FIFO_TPC_HALF_FULL = 74,
	IN_FIFO_TPC_FULL = 75,
	TPC_TC_XFC = 76,
	TPC_TC_STATE = 77,
	TC_STALL = 78,
	QUAD0_TAPS = 79,
	QUADS = 83,
	TCA_SYNC_STALL = 84,
	TAG_STALL = 85,
	TCB_SYNC_STALL = 88,
	TCA_VALID = 89,
	PROBES_VALID = 90,
	MISS_STALL = 91,
	FETCH_FIFO_STALL = 92,
	TCO_STALL = 93,
	ANY_STALL = 94,
	TAG_MISSES = 95,
	TAG_HITS = 96,
	SUB_TAG_MISSES = 97,
	SET0_INVALIDATES = 98,
	SET1_INVALIDATES = 99,
	SET2_INVALIDATES = 100,
	SET3_INVALIDATES = 101,
	SET0_TAG_MISSES = 102,
	SET1_TAG_MISSES = 103,
	SET2_TAG_MISSES = 104,
	SET3_TAG_MISSES = 105,
	SET0_TAG_HITS = 106,
	SET1_TAG_HITS = 107,
	SET2_TAG_HITS = 108,
	SET3_TAG_HITS = 109,
	SET0_SUB_TAG_MISSES = 110,
	SET1_SUB_TAG_MISSES = 111,
	SET2_SUB_TAG_MISSES = 112,
	SET3_SUB_TAG_MISSES = 113,
	SET0_EVICT1 = 114,
	SET0_EVICT2 = 115,
	SET0_EVICT3 = 116,
	SET0_EVICT4 = 117,
	SET0_EVICT5 = 118,
	SET0_EVICT6 = 119,
	SET0_EVICT7 = 120,
	SET0_EVICT8 = 121,
	SET1_EVICT1 = 130,
	SET1_EVICT2 = 131,
	SET1_EVICT3 = 132,
	SET1_EVICT4 = 133,
	SET1_EVICT5 = 134,
	SET1_EVICT6 = 135,
	SET1_EVICT7 = 136,
	SET1_EVICT8 = 137,
	SET2_EVICT1 = 146,
	SET2_EVICT2 = 147,
	SET2_EVICT3 = 148,
	SET2_EVICT4 = 149,
	SET2_EVICT5 = 150,
	SET2_EVICT6 = 151,
	SET2_EVICT7 = 152,
	SET2_EVICT8 = 153,
	SET3_EVICT1 = 162,
	SET3_EVICT2 = 163,
	SET3_EVICT3 = 164,
	SET3_EVICT4 = 165,
	SET3_EVICT5 = 166,
	SET3_EVICT6 = 167,
	SET3_EVICT7 = 168,
	SET3_EVICT8 = 169,
	FF_EMPTY = 178,
	FF_LT_HALF_FULL = 179,
	FF_HALF_FULL = 180,
	FF_FULL = 181,
	FF_XFC = 182,
	FF_STALLED = 183,
	FG_MASKS = 184,
	FG_LEFT_MASKS = 185,
	FG_LEFT_MASK_STALLED = 186,
	FG_LEFT_NOT_DONE_STALL = 187,
	FG_LEFT_FG_STALL = 188,
	FG_LEFT_SECTORS = 189,
	FG0_REQUESTS = 195,
	FG0_STALLED = 196,
	MEM_REQ512 = 199,
	MEM_REQ_SENT = 200,
	MEM_LOCAL_READ_REQ = 202,
	TC0_MH_STALLED = 203,
};

enum a2xx_sq_perfcnt_select {
	SQ_PIXEL_VECTORS_SUB = 0,
	SQ_VERTEX_VECTORS_SUB = 1,
	SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
	SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
	SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
	SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
	SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
	SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
	SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
	SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
	SQ_EXPORT_CYCLES = 10,
	SQ_ALU_CST_WRITTEN = 11,
	SQ_TEX_CST_WRITTEN = 12,
	SQ_ALU_CST_STALL = 13,
	SQ_ALU_TEX_STALL = 14,
	SQ_INST_WRITTEN = 15,
	SQ_BOOLEAN_WRITTEN = 16,
	SQ_LOOPS_WRITTEN = 17,
	SQ_PIXEL_SWAP_IN = 18,
	SQ_PIXEL_SWAP_OUT = 19,
	SQ_VERTEX_SWAP_IN = 20,
	SQ_VERTEX_SWAP_OUT = 21,
	SQ_ALU_VTX_INST_ISSUED = 22,
	SQ_TEX_VTX_INST_ISSUED = 23,
	SQ_VC_VTX_INST_ISSUED = 24,
	SQ_CF_VTX_INST_ISSUED = 25,
	SQ_ALU_PIX_INST_ISSUED = 26,
	SQ_TEX_PIX_INST_ISSUED = 27,
	SQ_VC_PIX_INST_ISSUED = 28,
	SQ_CF_PIX_INST_ISSUED = 29,
	SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
	SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
	SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
	SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
	SQ_ALU_NOPS = 34,
	SQ_PRED_SKIP = 35,
	SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
	SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
	SQ_SYNC_TEX_STALL_VTX = 38,
	SQ_SYNC_VC_STALL_VTX = 39,
	SQ_CONSTANTS_USED_SIMD0 = 40,
	SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
	SQ_GPR_STALL_VTX = 42,
	SQ_GPR_STALL_PIX = 43,
	SQ_VTX_RS_STALL = 44,
	SQ_PIX_RS_STALL = 45,
	SQ_SX_PC_FULL = 46,
	SQ_SX_EXP_BUFF_FULL = 47,
	SQ_SX_POS_BUFF_FULL = 48,
	SQ_INTERP_QUADS = 49,
	SQ_INTERP_ACTIVE = 50,
	SQ_IN_PIXEL_STALL = 51,
	SQ_IN_VTX_STALL = 52,
	SQ_VTX_CNT = 53,
	SQ_VTX_VECTOR2 = 54,
	SQ_VTX_VECTOR3 = 55,
	SQ_VTX_VECTOR4 = 56,
	SQ_PIXEL_VECTOR1 = 57,
	SQ_PIXEL_VECTOR23 = 58,
	SQ_PIXEL_VECTOR4 = 59,
	SQ_CONSTANTS_USED_SIMD1 = 60,
	SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
	SQ_SX_MEM_EXP_FULL = 62,
	SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
	SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
	SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
	SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
	SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
	SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
	SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
	SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
	SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
	SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
	SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
	SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
	SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
	SQ_PERFCOUNT_VTX_POP_THREAD = 76,
	SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
	SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
	SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
	SQ_PERFCOUNT_PIX_POP_THREAD = 80,
	SQ_SYNC_TEX_STALL_PIX = 81,
	SQ_SYNC_VC_STALL_PIX = 82,
	SQ_CONSTANTS_USED_SIMD2 = 83,
	SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
	SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
	SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
	SQ_ALU0_FIFO_FULL_SIMD0 = 87,
	SQ_ALU1_FIFO_FULL_SIMD0 = 88,
	SQ_ALU0_FIFO_FULL_SIMD1 = 89,
	SQ_ALU1_FIFO_FULL_SIMD1 = 90,
	SQ_ALU0_FIFO_FULL_SIMD2 = 91,
	SQ_ALU1_FIFO_FULL_SIMD2 = 92,
	SQ_ALU0_FIFO_FULL_SIMD3 = 93,
	SQ_ALU1_FIFO_FULL_SIMD3 = 94,
	VC_PERF_STATIC = 95,
	VC_PERF_STALLED = 96,
	VC_PERF_STARVED = 97,
	VC_PERF_SEND = 98,
	VC_PERF_ACTUAL_STARVED = 99,
	PIXEL_THREAD_0_ACTIVE = 100,
	VERTEX_THREAD_0_ACTIVE = 101,
	PIXEL_THREAD_0_NUMBER = 102,
	VERTEX_THREAD_0_NUMBER = 103,
	VERTEX_EVENT_NUMBER = 104,
	PIXEL_EVENT_NUMBER = 105,
	PTRBUFF_EF_PUSH = 106,
	PTRBUFF_EF_POP_EVENT = 107,
	PTRBUFF_EF_POP_NEW_VTX = 108,
	PTRBUFF_EF_POP_DEALLOC = 109,
	PTRBUFF_EF_POP_PVECTOR = 110,
	PTRBUFF_EF_POP_PVECTOR_X = 111,
	PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
	PTRBUFF_PB_DEALLOC = 113,
	PTRBUFF_PI_STATE_PPB_POP = 114,
	PTRBUFF_PI_RTR = 115,
	PTRBUFF_PI_READ_EN = 116,
	PTRBUFF_PI_BUFF_SWAP = 117,
	PTRBUFF_SQ_FREE_BUFF = 118,
	PTRBUFF_SQ_DEC = 119,
	PTRBUFF_SC_VALID_CNTL_EVENT = 120,
	PTRBUFF_SC_VALID_IJ_XFER = 121,
	PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
	PTRBUFF_QUAL_NEW_VECTOR = 123,
	PTRBUFF_QUAL_EVENT = 124,
	PTRBUFF_END_BUFFER = 125,
	PTRBUFF_FILL_QUAD = 126,
	VERTS_WRITTEN_SPI = 127,
	TP_FETCH_INSTR_EXEC = 128,
	TP_FETCH_INSTR_REQ = 129,
	TP_DATA_RETURN = 130,
	SPI_WRITE_CYCLES_SP = 131,
	SPI_WRITES_SP = 132,
	SP_ALU_INSTR_EXEC = 133,
	SP_CONST_ADDR_TO_SQ = 134,
	SP_PRED_KILLS_TO_SQ = 135,
	SP_EXPORT_CYCLES_TO_SX = 136,
	SP_EXPORTS_TO_SX = 137,
	SQ_CYCLES_ELAPSED = 138,
	SQ_TCFS_OPT_ALLOC_EXEC = 139,
	SQ_TCFS_NO_OPT_ALLOC = 140,
	SQ_ALU0_NO_OPT_ALLOC = 141,
	SQ_ALU1_NO_OPT_ALLOC = 142,
	SQ_TCFS_ARB_XFC_CNT = 143,
	SQ_ALU0_ARB_XFC_CNT = 144,
	SQ_ALU1_ARB_XFC_CNT = 145,
	SQ_TCFS_CFS_UPDATE_CNT = 146,
	SQ_ALU0_CFS_UPDATE_CNT = 147,
	SQ_ALU1_CFS_UPDATE_CNT = 148,
	SQ_VTX_PUSH_THREAD_CNT = 149,
	SQ_VTX_POP_THREAD_CNT = 150,
	SQ_PIX_PUSH_THREAD_CNT = 151,
	SQ_PIX_POP_THREAD_CNT = 152,
	SQ_PIX_TOTAL = 153,
	SQ_PIX_KILLED = 154,
};

enum a2xx_sx_perfcnt_select {
	SX_EXPORT_VECTORS = 0,
	SX_DUMMY_QUADS = 1,
	SX_ALPHA_FAIL = 2,
	SX_RB_QUAD_BUSY = 3,
	SX_RB_COLOR_BUSY = 4,
	SX_RB_QUAD_STALL = 5,
	SX_RB_COLOR_STALL = 6,
};

enum a2xx_rbbm_perfcount1_sel {
	RBBM1_COUNT = 0,
	RBBM1_NRT_BUSY = 1,
	RBBM1_RB_BUSY = 2,
	RBBM1_SQ_CNTX0_BUSY = 3,
	RBBM1_SQ_CNTX17_BUSY = 4,
	RBBM1_VGT_BUSY = 5,
	RBBM1_VGT_NODMA_BUSY = 6,
	RBBM1_PA_BUSY = 7,
	RBBM1_SC_CNTX_BUSY = 8,
	RBBM1_TPC_BUSY = 9,
	RBBM1_TC_BUSY = 10,
	RBBM1_SX_BUSY = 11,
	RBBM1_CP_COHER_BUSY = 12,
	RBBM1_CP_NRT_BUSY = 13,
	RBBM1_GFX_IDLE_STALL = 14,
	RBBM1_INTERRUPT = 15,
};

enum a2xx_cp_perfcount_sel {
	ALWAYS_COUNT = 0,
	TRANS_FIFO_FULL = 1,
	TRANS_FIFO_AF = 2,
	RCIU_PFPTRANS_WAIT = 3,
	RCIU_NRTTRANS_WAIT = 6,
	CSF_NRT_READ_WAIT = 8,
	CSF_I1_FIFO_FULL = 9,
	CSF_I2_FIFO_FULL = 10,
	CSF_ST_FIFO_FULL = 11,
	CSF_RING_ROQ_FULL = 13,
	CSF_I1_ROQ_FULL = 14,
	CSF_I2_ROQ_FULL = 15,
	CSF_ST_ROQ_FULL = 16,
	MIU_TAG_MEM_FULL = 18,
	MIU_WRITECLEAN = 19,
	MIU_NRT_WRITE_STALLED = 22,
	MIU_NRT_READ_STALLED = 23,
	ME_WRITE_CONFIRM_FIFO_FULL = 24,
	ME_VS_DEALLOC_FIFO_FULL = 25,
	ME_PS_DEALLOC_FIFO_FULL = 26,
	ME_REGS_VS_EVENT_FIFO_FULL = 27,
	ME_REGS_PS_EVENT_FIFO_FULL = 28,
	ME_REGS_CF_EVENT_FIFO_FULL = 29,
	ME_MICRO_RB_STARVED = 30,
	ME_MICRO_I1_STARVED = 31,
	ME_MICRO_I2_STARVED = 32,
	ME_MICRO_ST_STARVED = 33,
	RCIU_RBBM_DWORD_SENT = 40,
	ME_BUSY_CLOCKS = 41,
	ME_WAIT_CONTEXT_AVAIL = 42,
	PFP_TYPE0_PACKET = 43,
	PFP_TYPE3_PACKET = 44,
	CSF_RB_WPTR_NEQ_RPTR = 45,
	CSF_I1_SIZE_NEQ_ZERO = 46,
	CSF_I2_SIZE_NEQ_ZERO = 47,
	CSF_RBI1I2_FETCHING = 48,
};

enum a2xx_rb_perfcnt_select {
	RBPERF_CNTX_BUSY = 0,
	RBPERF_CNTX_BUSY_MAX = 1,
	RBPERF_SX_QUAD_STARVED = 2,
	RBPERF_SX_QUAD_STARVED_MAX = 3,
	RBPERF_GA_GC_CH0_SYS_REQ = 4,
	RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
	RBPERF_GA_GC_CH1_SYS_REQ = 6,
	RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
	RBPERF_MH_STARVED = 8,
	RBPERF_MH_STARVED_MAX = 9,
	RBPERF_AZ_BC_COLOR_BUSY = 10,
	RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
	RBPERF_AZ_BC_Z_BUSY = 12,
	RBPERF_AZ_BC_Z_BUSY_MAX = 13,
	RBPERF_RB_SC_TILE_RTR_N = 14,
	RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
	RBPERF_RB_SC_SAMP_RTR_N = 16,
	RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
	RBPERF_RB_SX_QUAD_RTR_N = 18,
	RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
	RBPERF_RB_SX_COLOR_RTR_N = 20,
	RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
	RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
	RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
	RBPERF_ZXP_STALL = 24,
	RBPERF_ZXP_STALL_MAX = 25,
	RBPERF_EVENT_PENDING = 26,
	RBPERF_EVENT_PENDING_MAX = 27,
	RBPERF_RB_MH_VALID = 28,
	RBPERF_RB_MH_VALID_MAX = 29,
	RBPERF_SX_RB_QUAD_SEND = 30,
	RBPERF_SX_RB_COLOR_SEND = 31,
	RBPERF_SC_RB_TILE_SEND = 32,
	RBPERF_SC_RB_SAMPLE_SEND = 33,
	RBPERF_SX_RB_MEM_EXPORT = 34,
	RBPERF_SX_RB_QUAD_EVENT = 35,
	RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
	RBPERF_SC_RB_TILE_EVENT_ALL = 37,
	RBPERF_RB_SC_EZ_SEND = 38,
	RBPERF_RB_SX_INDEX_SEND = 39,
	RBPERF_GMEM_INTFO_RD = 40,
	RBPERF_GMEM_INTF1_RD = 41,
	RBPERF_GMEM_INTFO_WR = 42,
	RBPERF_GMEM_INTF1_WR = 43,
	RBPERF_RB_CP_CONTEXT_DONE = 44,
	RBPERF_RB_CP_CACHE_FLUSH = 45,
	RBPERF_ZPASS_DONE = 46,
	RBPERF_ZCMD_VALID = 47,
	RBPERF_CCMD_VALID = 48,
	RBPERF_ACCUM_GRANT = 49,
	RBPERF_ACCUM_C0_GRANT = 50,
	RBPERF_ACCUM_C1_GRANT = 51,
	RBPERF_ACCUM_FULL_BE_WR = 52,
	RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
	RBPERF_ACCUM_TIMEOUT_PULSE = 54,
	RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
	RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
};

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enum adreno_mmu_clnt_beh {
	BEH_NEVR = 0,
	BEH_TRAN_RNG = 1,
	BEH_TRAN_FLT = 2,
};

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enum sq_tex_clamp {
	SQ_TEX_WRAP = 0,
	SQ_TEX_MIRROR = 1,
	SQ_TEX_CLAMP_LAST_TEXEL = 2,
	SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3,
	SQ_TEX_CLAMP_HALF_BORDER = 4,
	SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5,
	SQ_TEX_CLAMP_BORDER = 6,
	SQ_TEX_MIRROR_ONCE_BORDER = 7,
};

enum sq_tex_swiz {
	SQ_TEX_X = 0,
	SQ_TEX_Y = 1,
	SQ_TEX_Z = 2,
	SQ_TEX_W = 3,
	SQ_TEX_ZERO = 4,
	SQ_TEX_ONE = 5,
};

enum sq_tex_filter {
	SQ_TEX_FILTER_POINT = 0,
	SQ_TEX_FILTER_BILINEAR = 1,
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	SQ_TEX_FILTER_BASEMAP = 2,
	SQ_TEX_FILTER_USE_FETCH_CONST = 3,
};

enum sq_tex_aniso_filter {
	SQ_TEX_ANISO_FILTER_DISABLED = 0,
	SQ_TEX_ANISO_FILTER_MAX_1_1 = 1,
	SQ_TEX_ANISO_FILTER_MAX_2_1 = 2,
	SQ_TEX_ANISO_FILTER_MAX_4_1 = 3,
	SQ_TEX_ANISO_FILTER_MAX_8_1 = 4,
	SQ_TEX_ANISO_FILTER_MAX_16_1 = 5,
	SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7,
};

enum sq_tex_dimension {
	SQ_TEX_DIMENSION_1D = 0,
	SQ_TEX_DIMENSION_2D = 1,
	SQ_TEX_DIMENSION_3D = 2,
	SQ_TEX_DIMENSION_CUBE = 3,
};

enum sq_tex_border_color {
	SQ_TEX_BORDER_COLOR_BLACK = 0,
	SQ_TEX_BORDER_COLOR_WHITE = 1,
	SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2,
	SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3,
};

enum sq_tex_sign {
	SQ_TEX_SIGN_UNISIGNED = 0,
	SQ_TEX_SIGN_SIGNED = 1,
	SQ_TEX_SIGN_UNISIGNED_BIASED = 2,
	SQ_TEX_SIGN_GAMMA = 3,
};

enum sq_tex_endian {
	SQ_TEX_ENDIAN_NONE = 0,
	SQ_TEX_ENDIAN_8IN16 = 1,
	SQ_TEX_ENDIAN_8IN32 = 2,
	SQ_TEX_ENDIAN_16IN32 = 3,
};

enum sq_tex_clamp_policy {
	SQ_TEX_CLAMP_POLICY_D3D = 0,
	SQ_TEX_CLAMP_POLICY_OGL = 1,
};

enum sq_tex_num_format {
	SQ_TEX_NUM_FORMAT_FRAC = 0,
	SQ_TEX_NUM_FORMAT_INT = 1,
};

enum sq_tex_type {
	SQ_TEX_TYPE_0 = 0,
	SQ_TEX_TYPE_1 = 1,
	SQ_TEX_TYPE_2 = 2,
	SQ_TEX_TYPE_3 = 3,
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};

#define REG_A2XX_RBBM_PATCH_RELEASE				0x00000001

#define REG_A2XX_RBBM_CNTL					0x0000003b

#define REG_A2XX_RBBM_SOFT_RESET				0x0000003c

#define REG_A2XX_CP_PFP_UCODE_ADDR				0x000000c0

#define REG_A2XX_CP_PFP_UCODE_DATA				0x000000c1

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#define REG_A2XX_MH_MMU_CONFIG					0x00000040
#define A2XX_MH_MMU_CONFIG_MMU_ENABLE				0x00000001
#define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE			0x00000002
#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK		0x00000030
#define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT		4
static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
{
	return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK;
}
#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK		0x000000c0
#define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT		6
static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
{
	return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK;
}
#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK		0x00000300
#define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT		8
static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
{
	return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK;
}
#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK		0x00000c00
#define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT		10
static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
{
	return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK;
}
#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK		0x00003000
#define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT		12
static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
{
	return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK;
}
#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK		0x0000c000
#define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT		14
static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
{
	return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK;
}
#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK		0x00030000
#define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT		16
static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
{
	return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK;
}
#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK		0x000c0000
#define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT		18
static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
{
	return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK;
}
#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK		0x00300000
#define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT		20
static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
{
	return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK;
}
#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK		0x00c00000
#define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT		22
static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
{
	return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK;
}
#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK		0x03000000
#define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT		24
static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val)
{
	return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK;
}

#define REG_A2XX_MH_MMU_VA_RANGE				0x00000041
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#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK		0x00000fff
#define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT		0
static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val)
{
	return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK;
}
#define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK			0xfffff000
#define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT			12
static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val)
{
	return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK;
}
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#define REG_A2XX_MH_MMU_PT_BASE					0x00000042

#define REG_A2XX_MH_MMU_PAGE_FAULT				0x00000043

#define REG_A2XX_MH_MMU_TRAN_ERROR				0x00000044

#define REG_A2XX_MH_MMU_INVALIDATE				0x00000045
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#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL			0x00000001
#define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC			0x00000002
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#define REG_A2XX_MH_MMU_MPU_BASE				0x00000046

#define REG_A2XX_MH_MMU_MPU_END					0x00000047

#define REG_A2XX_NQWAIT_UNTIL					0x00000394

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#define REG_A2XX_RBBM_PERFCOUNTER1_SELECT			0x00000395

#define REG_A2XX_RBBM_PERFCOUNTER1_LO				0x00000397

#define REG_A2XX_RBBM_PERFCOUNTER1_HI				0x00000398

#define REG_A2XX_RBBM_DEBUG					0x0000039b

#define REG_A2XX_RBBM_PM_OVERRIDE1				0x0000039c
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#define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE		0x00000001
#define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE		0x00000002
#define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE		0x00000004
#define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE		0x00000008
#define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE		0x00000010
#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE		0x00000020
#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE	0x00000040
#define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE	0x00000080
#define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE		0x00000100
#define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE		0x00000200
#define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE		0x00000400
#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE		0x00000800
#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE		0x00001000
#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE		0x00002000
#define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE		0x00004000
#define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE		0x00008000
#define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE		0x00010000
#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE		0x00020000
#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE		0x00040000
#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE	0x00080000
#define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE		0x00100000
#define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE		0x00200000
#define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE		0x00400000
#define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE		0x00800000
#define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE	0x01000000
#define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE		0x02000000
#define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE		0x04000000
#define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE		0x08000000
#define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE		0x10000000
#define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE		0x20000000
#define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE		0x40000000
#define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE	0x80000000
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#define REG_A2XX_RBBM_PM_OVERRIDE2				0x0000039d

#define REG_A2XX_RBBM_DEBUG_OUT					0x000003a0

#define REG_A2XX_RBBM_DEBUG_CNTL				0x000003a1

#define REG_A2XX_RBBM_READ_ERROR				0x000003b3

#define REG_A2XX_RBBM_INT_CNTL					0x000003b4
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#define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK			0x00000001
#define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK		0x00000002
#define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK			0x00080000
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#define REG_A2XX_RBBM_INT_STATUS				0x000003b5

#define REG_A2XX_RBBM_INT_ACK					0x000003b6

#define REG_A2XX_MASTER_INT_SIGNAL				0x000003b7
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#define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT			0x00000020
#define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT			0x04000000
#define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT			0x40000000
#define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT			0x80000000
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#define REG_A2XX_RBBM_PERIPHID1					0x000003f9

#define REG_A2XX_RBBM_PERIPHID2					0x000003fa

#define REG_A2XX_CP_PERFMON_CNTL				0x00000444

#define REG_A2XX_CP_PERFCOUNTER_SELECT				0x00000445

#define REG_A2XX_CP_PERFCOUNTER_LO				0x00000446

#define REG_A2XX_CP_PERFCOUNTER_HI				0x00000447

#define REG_A2XX_RBBM_STATUS					0x000005d0
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#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK			0x0000001f
#define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT			0
static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val)
{
	return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK;
}
#define A2XX_RBBM_STATUS_TC_BUSY				0x00000020
#define A2XX_RBBM_STATUS_HIRQ_PENDING				0x00000100
#define A2XX_RBBM_STATUS_CPRQ_PENDING				0x00000200
#define A2XX_RBBM_STATUS_CFRQ_PENDING				0x00000400
#define A2XX_RBBM_STATUS_PFRQ_PENDING				0x00000800
#define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA			0x00001000
#define A2XX_RBBM_STATUS_RBBM_WU_BUSY				0x00004000
#define A2XX_RBBM_STATUS_CP_NRT_BUSY				0x00010000
#define A2XX_RBBM_STATUS_MH_BUSY				0x00040000
#define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY			0x00080000
#define A2XX_RBBM_STATUS_SX_BUSY				0x00200000
#define A2XX_RBBM_STATUS_TPC_BUSY				0x00400000
#define A2XX_RBBM_STATUS_SC_CNTX_BUSY				0x01000000
#define A2XX_RBBM_STATUS_PA_BUSY				0x02000000
#define A2XX_RBBM_STATUS_VGT_BUSY				0x04000000
#define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY				0x08000000
#define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY				0x10000000
#define A2XX_RBBM_STATUS_RB_CNTX_BUSY				0x40000000
#define A2XX_RBBM_STATUS_GUI_ACTIVE				0x80000000
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#define REG_A2XX_MH_ARBITER_CONFIG				0x00000a40
#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK		0x0000003f
#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT		0
static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val)
{
	return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK;
}
#define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY		0x00000040
#define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE			0x00000080
#define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE		0x00000100
#define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL			0x00000200
#define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK			0x00001c00
#define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT			10
static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val)
{
	return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK;
}
#define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE		0x00002000
#define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE		0x00004000
#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE		0x00008000
#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK		0x003f0000
#define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT		16
static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val)
{
	return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK;
}
#define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE			0x00400000
#define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE			0x00800000
#define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE			0x01000000
#define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE			0x02000000
#define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE			0x04000000

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#define REG_A2XX_MH_INTERRUPT_MASK				0x00000a42
#define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR			0x00000001
#define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR			0x00000002
#define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT			0x00000004

#define REG_A2XX_MH_INTERRUPT_STATUS				0x00000a43

#define REG_A2XX_MH_INTERRUPT_CLEAR				0x00000a44

#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1			0x00000a54

#define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2			0x00000a55

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#define REG_A2XX_A220_VSC_BIN_SIZE				0x00000c01
#define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK			0x0000001f
#define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT			0
static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val)
{
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	assert(!(val & 0x1f));
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	return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK;
}
#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK			0x000003e0
#define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT			5
static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val)
{
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	return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK;
}

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static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
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static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
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static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
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static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
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#define REG_A2XX_PC_DEBUG_CNTL					0x00000c38

#define REG_A2XX_PC_DEBUG_DATA					0x00000c39

#define REG_A2XX_PA_SC_VIZ_QUERY_STATUS				0x00000c44

#define REG_A2XX_GRAS_DEBUG_CNTL				0x00000c80

#define REG_A2XX_PA_SU_DEBUG_CNTL				0x00000c80

#define REG_A2XX_GRAS_DEBUG_DATA				0x00000c81

#define REG_A2XX_PA_SU_DEBUG_DATA				0x00000c81

#define REG_A2XX_PA_SU_FACE_DATA				0x00000c86
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#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK			0xffffffe0
#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT			5
static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val)
{
	return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK;
}
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#define REG_A2XX_SQ_GPR_MANAGEMENT				0x00000d00
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#define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC			0x00000001
#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK		0x00000ff0
#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT		4
static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val)
{
	return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK;
}
#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK		0x000ff000
#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT		12
static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val)
{
	return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK;
}
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#define REG_A2XX_SQ_FLOW_CONTROL				0x00000d01

#define REG_A2XX_SQ_INST_STORE_MANAGMENT			0x00000d02
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#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK	0x00000fff
#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT	0
static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val)
{
	return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK;
}
#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK	0x0fff0000
#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT	16
static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val)
{
	return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK;
}
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#define REG_A2XX_SQ_DEBUG_MISC					0x00000d05

#define REG_A2XX_SQ_INT_CNTL					0x00000d34

#define REG_A2XX_SQ_INT_STATUS					0x00000d35

#define REG_A2XX_SQ_INT_ACK					0x00000d36

#define REG_A2XX_SQ_DEBUG_INPUT_FSM				0x00000dae

#define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM				0x00000daf

#define REG_A2XX_SQ_DEBUG_TP_FSM				0x00000db0

#define REG_A2XX_SQ_DEBUG_FSM_ALU_0				0x00000db1

#define REG_A2XX_SQ_DEBUG_FSM_ALU_1				0x00000db2

#define REG_A2XX_SQ_DEBUG_EXP_ALLOC				0x00000db3

#define REG_A2XX_SQ_DEBUG_PTR_BUFF				0x00000db4

#define REG_A2XX_SQ_DEBUG_GPR_VTX				0x00000db5

#define REG_A2XX_SQ_DEBUG_GPR_PIX				0x00000db6

#define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL				0x00000db7

#define REG_A2XX_SQ_DEBUG_VTX_TB_0				0x00000db8

#define REG_A2XX_SQ_DEBUG_VTX_TB_1				0x00000db9

#define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG			0x00000dba

#define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM			0x00000dbb

#define REG_A2XX_SQ_DEBUG_PIX_TB_0				0x00000dbc

#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0			0x00000dbd

#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1			0x00000dbe

#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2			0x00000dbf

#define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3			0x00000dc0

#define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM			0x00000dc1

#define REG_A2XX_TC_CNTL_STATUS					0x00000e00
#define A2XX_TC_CNTL_STATUS_L2_INVALIDATE			0x00000001

#define REG_A2XX_TP0_CHICKEN					0x00000e1e

#define REG_A2XX_RB_BC_CONTROL					0x00000f01
#define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE		0x00000001
#define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK		0x00000006
#define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT		1
static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val)
{
	return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK;
}
#define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM			0x00000008
#define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH	0x00000010
#define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP		0x00000020
#define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP		0x00000040
#define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE			0x00000080
#define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK		0x00001f00
#define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT		8
static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val)
{
	return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK;
}
#define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE			0x00004000
#define A2XX_RB_BC_CONTROL_CRC_MODE				0x00008000
#define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS		0x00010000
#define A2XX_RB_BC_CONTROL_DISABLE_ACCUM			0x00020000
#define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK		0x003c0000
#define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT		18
static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val)
{
	return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK;
}
#define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE		0x00400000
#define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK		0x07800000
#define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT		23
static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val)
{
	return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK;
}
#define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK	0x18000000
#define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT	27
static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val)
{
	return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK;
}
#define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE	0x20000000
#define A2XX_RB_BC_CONTROL_CRC_SYSTEM				0x40000000
#define A2XX_RB_BC_CONTROL_RESERVED6				0x80000000

#define REG_A2XX_RB_EDRAM_INFO					0x00000f02

#define REG_A2XX_RB_DEBUG_CNTL					0x00000f26

#define REG_A2XX_RB_DEBUG_DATA					0x00000f27

#define REG_A2XX_RB_SURFACE_INFO				0x00002000
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#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK		0x00003fff
#define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT		0
static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val)
{
	return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK;
}
#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK			0x0000c000
#define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT		14
static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val)
{
	return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK;
}
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#define REG_A2XX_RB_COLOR_INFO					0x00002001
#define A2XX_RB_COLOR_INFO_FORMAT__MASK				0x0000000f
#define A2XX_RB_COLOR_INFO_FORMAT__SHIFT			0
static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val)
{
	return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK;
}
#define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK			0x00000030
#define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT			4
static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val)
{
	return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK;
}
#define A2XX_RB_COLOR_INFO_LINEAR				0x00000040
#define A2XX_RB_COLOR_INFO_ENDIAN__MASK				0x00000180
#define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT			7
static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val)
{
	return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK;
}
#define A2XX_RB_COLOR_INFO_SWAP__MASK				0x00000600
#define A2XX_RB_COLOR_INFO_SWAP__SHIFT				9
static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val)
{
	return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK;
}
#define A2XX_RB_COLOR_INFO_BASE__MASK				0xfffff000
#define A2XX_RB_COLOR_INFO_BASE__SHIFT				12
static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val)
{
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	assert(!(val & 0xfff));
	return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK;
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}

#define REG_A2XX_RB_DEPTH_INFO					0x00002002
#define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK			0x00000001
#define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT			0
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static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
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{
	return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
}
#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK			0xfffff000
#define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT			12
static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
{
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	assert(!(val & 0xfff));
	return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
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}

#define REG_A2XX_A225_RB_COLOR_INFO3				0x00002005

#define REG_A2XX_COHER_DEST_BASE_0				0x00002006

#define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL			0x0000200e
#define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
#define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK			0x00007fff
#define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT			0
static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
{
	return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK;
}
#define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK			0x7fff0000
#define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT			16
static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
{
	return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK;
}

#define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR			0x0000200f
#define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
#define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK			0x00007fff
#define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT			0
static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
{
	return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK;
}
#define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK			0x7fff0000
#define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT			16
static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
{
	return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK;
}

#define REG_A2XX_PA_SC_WINDOW_OFFSET				0x00002080
#define A2XX_PA_SC_WINDOW_OFFSET_X__MASK			0x00007fff
#define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT			0
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static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val)
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{
	return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK;
}
#define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK			0x7fff0000
#define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT			16
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static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val)
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{
	return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK;
}
#define A2XX_PA_SC_WINDOW_OFFSET_DISABLE			0x80000000

#define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL			0x00002081
#define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE	0x80000000
#define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK			0x00007fff
#define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT			0
static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
{
	return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK;
}
#define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK			0x7fff0000
#define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT			16
static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
{
	return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK;
}

#define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR			0x00002082
#define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE	0x80000000
#define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK			0x00007fff
#define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT			0
static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
{
	return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK;
}
#define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK			0x7fff0000
#define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT			16
static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
{
	return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK;
}

#define REG_A2XX_UNKNOWN_2010					0x00002010

#define REG_A2XX_VGT_MAX_VTX_INDX				0x00002100

#define REG_A2XX_VGT_MIN_VTX_INDX				0x00002101

#define REG_A2XX_VGT_INDX_OFFSET				0x00002102

#define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX		0x00002103

#define REG_A2XX_RB_COLOR_MASK					0x00002104
#define A2XX_RB_COLOR_MASK_WRITE_RED				0x00000001
#define A2XX_RB_COLOR_MASK_WRITE_GREEN				0x00000002
#define A2XX_RB_COLOR_MASK_WRITE_BLUE				0x00000004
#define A2XX_RB_COLOR_MASK_WRITE_ALPHA				0x00000008

#define REG_A2XX_RB_BLEND_RED					0x00002105

#define REG_A2XX_RB_BLEND_GREEN					0x00002106

#define REG_A2XX_RB_BLEND_BLUE					0x00002107

#define REG_A2XX_RB_BLEND_ALPHA					0x00002108

#define REG_A2XX_RB_FOG_COLOR					0x00002109
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#define A2XX_RB_FOG_COLOR_FOG_RED__MASK				0x000000ff
#define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT			0
static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val)
{
	return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK;
}
#define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK			0x0000ff00
#define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT			8
static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val)
{
	return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK;
}
#define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK			0x00ff0000
#define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT			16
static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val)
{
	return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK;
}
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#define REG_A2XX_RB_STENCILREFMASK_BF				0x0000210c
#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK		0x000000ff
#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT		0
static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
{
	return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
}
#define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK		0x0000ff00
#define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT		8
static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
{
	return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
}
#define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK	0x00ff0000
#define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT	16
static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
{
	return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
}

#define REG_A2XX_RB_STENCILREFMASK				0x0000210d
#define A2XX_RB_STENCILREFMASK_STENCILREF__MASK			0x000000ff
#define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT		0
static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
{
	return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK;
}
#define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK		0x0000ff00
#define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT		8
static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
{
	return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK;
}
#define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK		0x00ff0000
#define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT		16
static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
{
	return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
}

#define REG_A2XX_RB_ALPHA_REF					0x0000210e

#define REG_A2XX_PA_CL_VPORT_XSCALE				0x0000210f
#define A2XX_PA_CL_VPORT_XSCALE__MASK				0xffffffff
#define A2XX_PA_CL_VPORT_XSCALE__SHIFT				0
static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val)
{
	return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK;
}

#define REG_A2XX_PA_CL_VPORT_XOFFSET				0x00002110
#define A2XX_PA_CL_VPORT_XOFFSET__MASK				0xffffffff
#define A2XX_PA_CL_VPORT_XOFFSET__SHIFT				0
static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val)
{
	return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK;
}

#define REG_A2XX_PA_CL_VPORT_YSCALE				0x00002111
#define A2XX_PA_CL_VPORT_YSCALE__MASK				0xffffffff
#define A2XX_PA_CL_VPORT_YSCALE__SHIFT				0
static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val)
{
	return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK;
}

#define REG_A2XX_PA_CL_VPORT_YOFFSET				0x00002112
#define A2XX_PA_CL_VPORT_YOFFSET__MASK				0xffffffff
#define A2XX_PA_CL_VPORT_YOFFSET__SHIFT				0
static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val)
{
	return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK;
}

#define REG_A2XX_PA_CL_VPORT_ZSCALE				0x00002113
#define A2XX_PA_CL_VPORT_ZSCALE__MASK				0xffffffff
#define A2XX_PA_CL_VPORT_ZSCALE__SHIFT				0
static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val)
{
	return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK;
}

#define REG_A2XX_PA_CL_VPORT_ZOFFSET				0x00002114
#define A2XX_PA_CL_VPORT_ZOFFSET__MASK				0xffffffff
#define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT				0
static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val)
{
	return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK;
}

#define REG_A2XX_SQ_PROGRAM_CNTL				0x00002180
#define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK			0x000000ff
#define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT			0
static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val)
{
	return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK;
}
#define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK			0x0000ff00
#define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT			8
static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val)
{
	return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK;
}
#define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE			0x00010000
#define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE			0x00020000
#define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN				0x00040000
#define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX			0x00080000
#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK		0x00f00000
#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT		20
static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val)
{
	return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK;
}
#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK		0x07000000
#define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT		24
static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val)
{
	return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK;
}
#define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK		0x78000000
#define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT		27
static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val)
{
	return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK;
}
#define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX			0x80000000

#define REG_A2XX_SQ_CONTEXT_MISC				0x00002181
#define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE			0x00000001
#define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY		0x00000002
#define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK		0x0000000c
#define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT		2
static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val)
{
	return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK;
}
#define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK		0x0000ff00
#define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT		8
static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
{
	return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK;
}
#define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF			0x00010000
#define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE			0x00020000
#define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL			0x00040000

#define REG_A2XX_SQ_INTERPOLATOR_CNTL				0x00002182
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#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK		0x0000ffff
#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT		0
static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val)
{
	return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK;
}
#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK	0xffff0000
#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT	16
static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val)
{
	return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK;
}
1743 1744

#define REG_A2XX_SQ_WRAPPING_0					0x00002183
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#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK			0x0000000f
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT			0
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK			0x000000f0
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT			4
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK			0x00000f00
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT			8
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK			0x0000f000
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT			12
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK			0x000f0000
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT			16
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK			0x00f00000
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT			20
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK			0x0f000000
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT			24
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK			0xf0000000
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT			28
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK;
}
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#define REG_A2XX_SQ_WRAPPING_1					0x00002184
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#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK			0x0000000f
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT			0
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK			0x000000f0
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT			4
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK			0x00000f00
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT			8
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK			0x0000f000
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT			12
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK			0x000f0000
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT			16
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK			0x00f00000
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT			20
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK			0x0f000000
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT			24
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK			0xf0000000
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT			28
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val)
{
	return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK;
}
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#define REG_A2XX_SQ_PS_PROGRAM					0x000021f6
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#define A2XX_SQ_PS_PROGRAM_BASE__MASK				0x00000fff
#define A2XX_SQ_PS_PROGRAM_BASE__SHIFT				0
static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val)
{
	return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK;
}
#define A2XX_SQ_PS_PROGRAM_SIZE__MASK				0x00fff000
#define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT				12
static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val)
{
	return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK;
}
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#define REG_A2XX_SQ_VS_PROGRAM					0x000021f7
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#define A2XX_SQ_VS_PROGRAM_BASE__MASK				0x00000fff
#define A2XX_SQ_VS_PROGRAM_BASE__SHIFT				0
static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val)
{
	return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK;
}
#define A2XX_SQ_VS_PROGRAM_SIZE__MASK				0x00fff000
#define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT				12
static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val)
{
	return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK;
}
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#define REG_A2XX_VGT_EVENT_INITIATOR				0x000021f9

#define REG_A2XX_VGT_DRAW_INITIATOR				0x000021fc
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#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK			0x0000003f
#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT		0
static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
{
	return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
}
#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK		0x000000c0
#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT		6
static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
{
	return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
}
#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK			0x00000600
#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT			9
static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
{
	return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
}
#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK		0x00000800
#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT		11
static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
{
	return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
}
#define A2XX_VGT_DRAW_INITIATOR_NOT_EOP				0x00001000
#define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX			0x00002000
#define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE	0x00004000
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#define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK		0xff000000
#define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT		24
static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
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{
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	return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;
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}
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#define REG_A2XX_VGT_IMMED_DATA					0x000021fd

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#define REG_A2XX_RB_DEPTHCONTROL				0x00002200
#define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE			0x00000001
#define A2XX_RB_DEPTHCONTROL_Z_ENABLE				0x00000002
#define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE			0x00000004
#define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE			0x00000008
#define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK			0x00000070
#define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT			4
static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val)
{
	return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK;
}
#define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE			0x00000080
#define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK			0x00000700
#define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT			8
static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val)
{
	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK;
}
#define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK			0x00003800
#define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT			11
static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val)
{
	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK;
}
#define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK			0x0001c000
#define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT		14
static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val)
{
	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK;
}
#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK			0x000e0000
#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT		17
static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val)
{
	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK;
}
#define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK		0x00700000
#define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT		20
static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val)
{
	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK;
}
#define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK		0x03800000
#define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT		23
static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val)
{
	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK;
}
#define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK		0x1c000000
#define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT		26
static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val)
{
	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK;
}
#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK		0xe0000000
#define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT		29
static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val)
{
	return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK;
}

#define REG_A2XX_RB_BLEND_CONTROL				0x00002201
#define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK		0x0000001f
#define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT		0
static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val)
{
	return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK;
}
#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK		0x000000e0
#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT		5
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1981
static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)
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{
	return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;
}
#define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK		0x00001f00
#define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT		8
static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val)
{
	return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK;
}
#define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK		0x001f0000
#define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT		16
static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val)
{
	return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK;
}
#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK		0x00e00000
#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT		21
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static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)
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{
	return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;
}
#define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK		0x1f000000
#define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT		24
static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val)
{
	return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK;
}
#define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE		0x20000000
#define A2XX_RB_BLEND_CONTROL_BLEND_FORCE			0x40000000

#define REG_A2XX_RB_COLORCONTROL				0x00002202
#define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK			0x00000007
#define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT			0
static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val)
{
	return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK;
}
#define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE			0x00000008
#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE		0x00000010
#define A2XX_RB_COLORCONTROL_BLEND_DISABLE			0x00000020
#define A2XX_RB_COLORCONTROL_VOB_ENABLE				0x00000040
#define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG			0x00000080
#define A2XX_RB_COLORCONTROL_ROP_CODE__MASK			0x00000f00
#define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT			8
static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val)
{
	return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK;
}
#define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK			0x00003000
#define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT			12
static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
{
	return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK;
}
#define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK			0x0000c000
#define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT			14
static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val)
{
	return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK;
}
#define A2XX_RB_COLORCONTROL_PIXEL_FOG				0x00010000
#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK	0x03000000
#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT	24
static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val)
{
	return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK;
}
#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK	0x0c000000
#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT	26
static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val)
{
	return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK;
}
#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK	0x30000000
#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT	28
static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val)
{
	return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK;
}
#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK	0xc0000000
#define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT	30
static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val)
{
	return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK;
}

#define REG_A2XX_VGT_CURRENT_BIN_ID_MAX				0x00002203
#define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK		0x00000007
#define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT		0
static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val)
{
	return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK;
}
#define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK			0x00000038
#define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT			3
static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val)
{
	return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK;
}
#define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK	0x000001c0
#define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT	6
static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val)
{
	return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK;
}

#define REG_A2XX_PA_CL_CLIP_CNTL				0x00002204
#define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE			0x00010000
#define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA		0x00040000
#define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK		0x00080000
#define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT		19
static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val)
{
	return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK;
}
#define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT		0x00100000
#define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR			0x00200000
#define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN			0x00400000
#define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN			0x00800000
#define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN			0x01000000

#define REG_A2XX_PA_SU_SC_MODE_CNTL				0x00002205
#define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT			0x00000001
#define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK			0x00000002
#define A2XX_PA_SU_SC_MODE_CNTL_FACE				0x00000004
#define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK			0x00000018