• Stephen Boyd's avatar
    Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and... · ffe05540
    Stephen Boyd authored
    Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and 'clk-rockchip' into clk-next
    * clk-renesas:
      clk: renesas: rcar-gen3: Add HS400 quirk for SD clock
      clk: renesas: rcar-gen3: Add documentation for SD clocks
      clk: renesas: rcar-gen3: Set state when registering SD clocks
      clk: renesas: r8a77995: Simplify PLL3 multiplier/divider
      clk: renesas: r8a77995: Add missing CPEX clock
      clk: renesas: r8a77995: Remove non-existent SSP clocks
      clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks
      clk: renesas: r8a77995: Correct parent clock of DU
      clk: renesas: r8a77990: Correct parent clock of DU
      clk: renesas: r8a77970: Add CPEX clock
      clk: renesas: r8a77965: Add CPEX clock
      clk: renesas: r8a7796: Add CPEX clock
      clk: renesas: r8a7795: Add CPEX clock
      clk: renesas: r8a774a1: Add CPEX clock
      dt-bindings: clock: r8a7796: Remove CSIREF clock
      dt-bindings: clock: r8a7795: Remove CSIREF clock
      clk: renesas: Mark rza2_cpg_clk_register static
      clk: renesas: r7s9210: Add USB clocks
      clk: renesas: r8a77970: Add RPC clocks
      clk: renesas: r7s9210: Add SDHI clocks
    * clk-allwinner:
      clk: sunxi-ng: a64: Allow parent change for VE clock
      clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks
      clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL
      clk: sunxi-ng: h3: Allow parent change for ve clock
      clk: sunxi-ng: add support for suniv F1C100s SoC
      dt-bindings: clock: Add Allwinner suniv F1C100s CCU
      clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent
      clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output
      clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL
      clk: sunxi-ng: a64: Fix gate bit of DSI DPHY
      clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I
      clk: sunxi-ng: Add support for H6 DE3 clocks
      dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description
      clk: sunxi-ng: h6: Set video PLLs limits
      clk: sunxi-ng: Use u64 for calculation of NM rate
      clk: sunxi-ng: Adjust MP clock parent rate when allowed
      clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width
      clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock
    * clk-tegra:
      clk: tegra: Return the exact clock rate from clk_round_rate
      clk: tegra30: Use Tegra CPU powergate helper function
      soc/tegra: pmc: Drop SMP dependency from CPU APIs
      clk: tegra: Fix maximum audio sync clock for Tegra124/210
      clk: tegra: get rid of duplicate defines
      clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC
      clk: tegra20: Turn EMC clock gate into divider
    * clk-meson: (25 commits)
      clk: meson: axg-audio: use the clk input helper function
      clk: meson: add clk-input helper function
      clk: meson: Mark some things static
      clk: meson: meson8b: add the read-only video clock trees
      clk: meson: meson8b: add the fractional divider for vid_pll_dco
      clk: meson: meson8b: fix the offset of vid_pll_dco's N value
      clk: meson: Fix GXL HDMI PLL fractional bits width
      clk: meson: meson8b: add the CPU clock post divider clocks
      clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3
      clk: meson: clk-regmap: add read-only gate ops
      clk: meson: meson8b: allow changing the CPU clock tree
      clk: meson: meson8b: run from the XTAL when changing the CPU frequency
      clk: meson: meson8b: add support for more M/N values in sys_pll
      clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL
      clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel
      clk: meson: clk-pll: check if the clock is already enabled
      clk: meson: meson8b: fix the width of the cpu_scale_div clock
      clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table
      clk: meson: meson8b: use the HHI syscon if available
      dt-bindings: clock: meson8b: use the registers from the HHI syscon
    * clk-rockchip:
      clk: rockchip: add clock-id to gate of ACODEC for rk3328
      clk: rockchip: add clock ID of ACODEC for rk3328
      clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328
      clk: rockchip: fix I2S1 clock gate register for rk3328
      clk: rockchip: make rk3188 hclk_vio_bus critical
      clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering
      clk: rockchip: fix rk3188 sclk_smc gate data
      clk: rockchip: fix typo in rk3188 spdif_frac parent
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clk-audio-sync.c Loading commit data...
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clk-dfll.c Loading commit data...
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clk-divider.c Loading commit data...
clk-emc.c Loading commit data...
clk-id.h Loading commit data...
clk-periph-fixed.c Loading commit data...
clk-periph-gate.c Loading commit data...
clk-periph.c Loading commit data...
clk-pll-out.c Loading commit data...
clk-pll.c Loading commit data...
clk-sdmmc-mux.c Loading commit data...
clk-super.c Loading commit data...
clk-tegra-audio.c Loading commit data...
clk-tegra-fixed.c Loading commit data...
clk-tegra-periph.c Loading commit data...
clk-tegra-pmc.c Loading commit data...
clk-tegra-super-gen4.c Loading commit data...
clk-tegra114.c Loading commit data...
clk-tegra124-dfll-fcpu.c Loading commit data...
clk-tegra124.c Loading commit data...
clk-tegra20.c Loading commit data...
clk-tegra210.c Loading commit data...
clk-tegra30.c Loading commit data...
clk-utils.c Loading commit data...
clk.c Loading commit data...
clk.h Loading commit data...
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