• Catalin Marinas's avatar
    arm64: Add workaround for Cortex-A76 erratum 1286807 · ce8c80c5
    Catalin Marinas authored
    On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual address
    for a cacheable mapping of a location is being accessed by a core while
    another core is remapping the virtual address to a new physical page
    using the recommended break-before-make sequence, then under very rare
    circumstances TLBI+DSB completes before a read using the translation
    being invalidated has been observed by other observers. The workaround
    repeats the TLBI+DSB operation and is shared with the Qualcomm Falkor
    erratum 1009
    Reviewed-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
    Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
    ce8c80c5
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