1. 14 Dec, 2018 2 commits
  2. 10 Dec, 2018 1 commit
  3. 16 Oct, 2018 1 commit
  4. 09 Oct, 2018 1 commit
  5. 06 Jul, 2018 1 commit
    • Daniel Mack's avatar
      clk: Add driver for MAX9485 · 33f51046
      Daniel Mack authored
      This patch adds a driver for MAX9485, a programmable audio clock generator.
      
      The device requires a 27.000 MHz clock input. It can provide a gated
      buffered output of its input clock and two gated outputs of a PLL that can
      generate one out of 16 discrete frequencies. There is only one PLL however,
      so the two gated outputs will always have the same frequency but they can
      be switched individually.
      
      The driver for this device exposes 4 clocks in total:
      
      - MAX9485_MCLKOUT:      A gated, buffered output of the input clock
      - MAX9485_CLKOUT:       A PLL that can be configured to 16 different
      			discrete frequencies
      - MAX9485_CLKOUT[1,2]:  Two gated outputs for MAX9485_CLKOUT
      
      Some PLL output frequencies can be achieved with different register
      settings. The driver will select the one with lowest jitter in such cases.
      Signed-off-by: default avatarDaniel Mack <daniel@zonque.org>
      [sboyd@kernel.org: Use local variable for val in max9485_clkout_recalc_rate()
      and shorten line of max9485_of_clk_get()]
      Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
      33f51046
  6. 15 May, 2018 1 commit
  7. 06 Apr, 2018 1 commit
  8. 23 Mar, 2018 1 commit
  9. 19 Mar, 2018 2 commits
  10. 11 Mar, 2018 1 commit
  11. 28 Feb, 2018 1 commit
    • Sudeep Holla's avatar
      clk: add support for clocks provided by SCMI · 6d6a1d82
      Sudeep Holla authored
      On some ARM based systems, a separate Cortex-M based System Control
      Processor(SCP) provides the overall power, clock, reset and system
      control. System Control and Management Interface(SCMI) Message Protocol
      is defined for the communication between the Application Cores(AP)
      and the SCP.
      
      This patch adds support for the clocks provided by SCP using SCMI
      protocol.
      
      Cc: linux-clk@vger.kernel.org
      Cc: Michael Turquette <mturquette@baylibre.com>
      Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
      6d6a1d82
  12. 27 Jan, 2018 1 commit
  13. 21 Dec, 2017 1 commit
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  15. 17 Jul, 2017 1 commit
  16. 11 Jul, 2017 1 commit
  17. 21 Jun, 2017 1 commit
  18. 14 Jun, 2017 1 commit
    • Tero Kristo's avatar
      clk: keystone: Add sci-clk driver support · b745c079
      Tero Kristo authored
      In K2G, the clock handling is done through firmware executing on a
      separate core. Linux kernel needs to communicate to the firmware
      through TI system control interface to access any power management
      related resources, including clocks.
      
      The keystone sci-clk driver does this, by communicating to the
      firmware through the TI SCI driver. The driver adds support for
      registering clocks through DT, and basic required clock operations
      like prepare/get_rate, etc.
      Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
      [sboyd@codeaurora.org: Make ti_sci_init_clocks() static]
      Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      b745c079
  19. 22 Apr, 2017 1 commit
  20. 21 Jan, 2017 1 commit
  21. 10 Jan, 2017 1 commit
  22. 02 Nov, 2016 1 commit
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  25. 15 Aug, 2016 2 commits
  26. 12 Jul, 2016 1 commit
  27. 09 Jul, 2016 1 commit
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  32. 21 Apr, 2016 1 commit
  33. 20 Apr, 2016 1 commit
  34. 02 Mar, 2016 1 commit
    • Tony Lindgren's avatar
      clk: ti: Add support for dm814x ADPLL · 21330497
      Tony Lindgren authored
      On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The
      ADPLLs have several dividers and muxes controlled by a shared
      control register for each PLL.
      
      Note that for the clocks to work as device drivers for booting on
      dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall
      levels to postcore_initcall" that has already been merged.
      
      Also note that this patch does not implement clk_set_rate for the
      PLL, that will be posted later on when available.
      
      Cc: Stephen Boyd <sboyd@codeaurora.org>
      Acked-by: default avatarTero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
      21330497
  35. 25 Feb, 2016 1 commit
  36. 08 Feb, 2016 1 commit