1. 27 Aug, 2018 1 commit
  2. 14 Feb, 2017 1 commit
  3. 28 Jan, 2017 2 commits
  4. 15 Dec, 2016 1 commit
  5. 01 Dec, 2016 1 commit
    • Borislav Petkov's avatar
      EDAC, amd64: Improve amd64-specific printing macros · 5246c540
      Borislav Petkov authored
      Prefix the warn and error macros with the respective string so that
      callers don't have to say "Error" or "Warning". We save us string length
      this way in the actual calls.
      
      While at it, shorten the calls in reserve_mc_sibling_devs().
      Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
      Cc: Dan Carpenter <dan.carpenter@oracle.com>
      Cc: Yazen Ghannam <Yazen.Ghannam@amd.com>
      5246c540
  6. 29 Nov, 2016 2 commits
  7. 28 Nov, 2016 3 commits
  8. 24 Nov, 2016 2 commits
  9. 09 May, 2016 1 commit
    • Borislav Petkov's avatar
      EDAC, amd64_edac: Drop pci_register_driver() use · 3f37a36b
      Borislav Petkov authored
      - remove homegrown instances counting.
      - take F3 PCI device from amd_nb caching instead of F2 which was used with the
      PCI core.
      
      With those changes, the driver doesn't need to register a PCI driver and
      relies on the northbridges caching which we do anyway on AMD.
      Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
      Cc: Yazen Ghannam <yazen.ghannam@amd.com>
      3f37a36b
  10. 29 Sep, 2015 2 commits
  11. 23 Feb, 2015 1 commit
  12. 30 Oct, 2014 1 commit
    • Aravind Gopalakrishnan's avatar
      amd64_edac: Add F15h M60h support · a597d2a5
      Aravind Gopalakrishnan authored
      This patch adds support for ECC error decoding for F15h M60h processor.
      Aside from the usual changes, the patch adds support for some new features
      in the processor:
       - DDR4(unbuffered, registered); LRDIMM DDR3 support
         - relevant debug messages have been modified/added to report these
           memory types
       - new dbam_to_cs mappers
         - if (F15h M60h && LRDIMM); we need a 'multiplier' value to find
           cs_size. This multiplier value is obtained from the per-dimm
           DCSM register. So, change the interface to accept a 'cs_mask_nr'
           value to facilitate this calculation
       - switch-casing determine_memory_type()
         - done to cleanse the function of too many if-else statements
           and improve readability
         - This is now called early in read_mc_regs() to cache dram_type
      
      Misc cleanup:
       - amd64_pci_table[] is condensed by using PCI_VDEVICE macro.
      
      Testing details:
      Tested the patch by injecting 'ECC' type errors using mce_amd_inj
      and error decoding works fine.
      Signed-off-by: default avatarAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
      Link: http://lkml.kernel.org/r/1414617483-4941-1-git-send-email-Aravind.Gopalakrishnan@amd.com
      [ Boris: determine_memory_type() cleanups ]
      Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
      a597d2a5
  13. 23 Sep, 2014 1 commit
    • Aravind Gopalakrishnan's avatar
      amd64_edac: Modify usage of amd64_read_dct_pci_cfg() · 7981a28f
      Aravind Gopalakrishnan authored
      Rationale behind this change:
       - F2x1xx addresses were stopped from being mapped explicitly to DCT1
         from F15h (OR) onwards. They use _dct[0:1] mechanism to access the
         registers. So we should move away from using address ranges to select
         DCT for these families.
       - On newer processors, the address ranges used to indicate DCT1 (0x140,
         0x1a0) have different meanings than what is assumed currently.
      
      Changes introduced:
       - amd64_read_dct_pci_cfg() now takes in dct value and uses it for
         'selecting the dct'
       - Update usage of the function. Keep in mind that different families
         have specific handling requirements
       - Remove [k8|f10]_read_dct_pci_cfg() as they don't do much different
         from amd64_read_pci_cfg()
         - Move the k8 specific check to amd64_read_pci_cfg
       - Remove f15_read_dct_pci_cfg() and move logic to amd64_read_dct_pci_cfg()
       - Remove now needless .read_dct_pci_cfg
      
      Testing:
       - Tested on Fam 10h; Fam15h Models: 00h, 30h; Fam16h using 'EDAC_DEBUG'
         and mce_amd_inj
       - driver obtains info from F2x registers and caches it in pvt
         structures correctly
       - ECC decoding works fine
      Signed-off-by: default avatarAravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
      Link: http://lkml.kernel.org/r/1410799058-3149-1-git-send-email-aravind.gopalakrishnan@amd.comSigned-off-by: default avatarBorislav Petkov <bp@suse.de>
      7981a28f
  14. 27 Feb, 2014 1 commit
  15. 21 Oct, 2013 1 commit
  16. 12 Aug, 2013 2 commits
    • Borislav Petkov's avatar
      amd64_edac: Get rid of boot_cpu_data accesses · a4b4bedc
      Borislav Petkov authored
      Now that we cache (family, model, stepping) locally, use them instead of
      boot_cpu_data.
      
      No functionality change.
      Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
      a4b4bedc
    • Aravind Gopalakrishnan's avatar
      amd64_edac: Add ECC decoding support for newer F15h models · 18b94f66
      Aravind Gopalakrishnan authored
      On newer models, support has been included for upto 4 DCT's, however,
      only DCT0 and DCT3 are currently configured (cf BKDG Section 2.10).
      Also, the routing DRAM Requests algorithm is different for F15h M30h.
      Thus it is cleaner to use a brand new function rather than adding quirks
      to the more generic f1x_match_to_this_node(). Refer to "2.10.5 DRAM
      Routing Requests" in the BKDG for further info.
      
      Tested on Fam15h M30h with ECC turned on using mce_amd_inj facility and
      verified to be functionally correct.
      
      While at it, verify if erratum workarounds for E505 and E637 still hold.
      From email conversations within AMD, the current status of the errata
      is:
      
            * Erratum 505: fixed in model 0x1, stepping 0x1 and later.
            * Erratum 637: not fixed.
      Signed-off-by: default avatarAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
      [ Cleanups, corrections ]
      Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
      18b94f66
  17. 19 Apr, 2013 1 commit
  18. 10 Jan, 2013 2 commits
  19. 28 Nov, 2012 4 commits
  20. 30 Oct, 2012 1 commit
  21. 11 Jun, 2012 1 commit
  22. 26 Apr, 2011 2 commits
    • Borislav Petkov's avatar
      amd64_edac: Erratum #637 workaround · c1ae6830
      Borislav Petkov authored
      F15h CPUs may report a non-DRAM address when reporting an error address
      belonging to a CC6 state save area. Add a workaround to detect this
      condition and compute the actual DRAM address of the error as documented
      in the Revision Guide for AMD Family 15h Models 00h-0Fh Processors.
      Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      c1ae6830
    • Borislav Petkov's avatar
      amd64_edac: Factor in CC6 save area · f08e457c
      Borislav Petkov authored
      F15h and later use a portion of DRAM as a CC6 storage area. BIOS
      programs D18F1x[17C:140,7C:40] DRAM Base/Limit accordingly by
      subtracting the storage area from the DRAM limit setting. However, in
      order for edac to consider that part of DRAM too, we need to include it
      into the per-node range.
      Signed-off-by: default avatarBorislav Petkov <borislav.petkov@amd.com>
      f08e457c
  23. 17 Mar, 2011 6 commits