1. 01 Jun, 2016 1 commit
  2. 13 May, 2016 1 commit
  3. 21 Apr, 2016 1 commit
  4. 20 Apr, 2016 1 commit
  5. 02 Mar, 2016 1 commit
    • Tony Lindgren's avatar
      clk: ti: Add support for dm814x ADPLL · 21330497
      Tony Lindgren authored
      On dm814x we have 13 ADPLLs with 3 to 4 outputs on each. The
      ADPLLs have several dividers and muxes controlled by a shared
      control register for each PLL.
      Note that for the clocks to work as device drivers for booting on
      dm814x, this patch depends on "ARM: OMAP2+: Change core_initcall
      levels to postcore_initcall" that has already been merged.
      Also note that this patch does not implement clk_set_rate for the
      PLL, that will be posted later on when available.
      Cc: Stephen Boyd <sboyd@codeaurora.org>
      Acked-by: default avatarTero Kristo <t-kristo@ti.com>
      Signed-off-by: default avatarTony Lindgren <tony@atomide.com>
      Signed-off-by: default avatarMichael Turquette <mturquette@baylibre.com>
  6. 25 Feb, 2016 1 commit
  7. 08 Feb, 2016 2 commits
  8. 30 Jan, 2016 1 commit
  9. 14 Jan, 2016 1 commit
  10. 24 Dec, 2015 2 commits
  11. 01 Dec, 2015 1 commit
  12. 21 Oct, 2015 1 commit
  13. 16 Oct, 2015 1 commit
  14. 09 Oct, 2015 1 commit
  15. 02 Oct, 2015 1 commit
  16. 28 Sep, 2015 1 commit
    • Sudeep Holla's avatar
      clk: add support for clocks provided by SCP(System Control Processor) · cd52c2a4
      Sudeep Holla authored
      On some ARM based systems, a separate Cortex-M based System Control
      Processor(SCP) provides the overall power, clock, reset and system
      control. System Control and Power Interface(SCPI) Message Protocol
      is defined for the communication between the Application Cores(AP)
      and the SCP.
      This patch adds support for the clocks provided by SCP using SCPI
      Signed-off-by: default avatarSudeep Holla <sudeep.holla@arm.com>
      Reviewed-by: default avatarStephen Boyd <sboyd@codeaurora.org>
      Cc: Mike Turquette <mturquette@baylibre.com>
      Cc: Liviu Dudau <Liviu.Dudau@arm.com>
      Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
      Cc: linux-clk@vger.kernel.org
  17. 03 Jun, 2015 2 commits
  18. 15 May, 2015 1 commit
  19. 13 May, 2015 1 commit
  20. 10 Apr, 2015 1 commit
  21. 20 Jan, 2015 1 commit
  22. 17 Jan, 2015 1 commit
  23. 06 Jan, 2015 1 commit
    • Pranith Kumar's avatar
      rcu: Make SRCU optional by using CONFIG_SRCU · 83fe27ea
      Pranith Kumar authored
      SRCU is not necessary to be compiled by default in all cases. For tinification
      efforts not compiling SRCU unless necessary is desirable.
      The current patch tries to make compiling SRCU optional by introducing a new
      Kconfig option CONFIG_SRCU which is selected when any of the components making
      use of SRCU are selected.
      If we do not select CONFIG_SRCU, srcu.o will not be compiled at all.
         text    data     bss     dec     hex filename
         2007       0       0    2007     7d7 kernel/rcu/srcu.o
      Size of arch/powerpc/boot/zImage changes from
         text    data     bss     dec     hex filename
       831552   64180   23944  919676   e087c arch/powerpc/boot/zImage : before
       829504   64180   23952  917636   e0084 arch/powerpc/boot/zImage : after
      so the savings are about ~2000 bytes.
      Signed-off-by: default avatarPranith Kumar <bobby.prani@gmail.com>
      CC: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
      CC: Josh Triplett <josh@joshtriplett.org>
      CC: Lai Jiangshan <laijs@cn.fujitsu.com>
      Signed-off-by: default avatarPaul E. McKenney <paulmck@linux.vnet.ibm.com>
      [ paulmck: resolve conflict due to removal of arch/ia64/kvm/Kconfig. ]
  24. 29 Oct, 2014 1 commit
  25. 14 Oct, 2014 1 commit
  26. 05 Oct, 2014 1 commit
  27. 09 Sep, 2014 3 commits
  28. 02 Jul, 2014 1 commit
    • Peter Ujfalusi's avatar
      clk: Add driver for Palmas clk32kg and clk32kgaudio clocks · 942d1d67
      Peter Ujfalusi authored
      Palmas class of devices can provide 32K clock(s) to be used by other devices
      on the board. Depending on the actual device the provided clocks can be:
      CLK32K_KG and CLK32K_KGAUDIO
      or only one:
      CLK32K_KG (TPS659039 for example)
      Use separate compatible flags for the two 32K clock.
      A system which needs or have only one of the 32k clock from
      Palmas will need to add node(s) for each clock as separate section
      in the dts file.
      The two compatible property is:
      "ti,palmas-clk32kg" for clk32kg clock
      "ti,palmas-clk32kgaudio" for clk32kgaudio clock
      Apart from the register control of the clocks - which is done via
      the clock API there is a posibility to enable the external sleep
      control. In this way the clock can be enabled/disabled on demand by the
      user of the clock.
      See the documentation for more details.
      Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
      Reviewed-by: default avatarNishanth Menon <nm@ti.com>
      Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
  29. 23 May, 2014 1 commit
  30. 15 May, 2014 1 commit
  31. 14 May, 2014 1 commit
  32. 19 Mar, 2014 1 commit
  33. 24 Feb, 2014 1 commit
    • Alex Elder's avatar
      clk: bcm281xx: add initial clock framework support · 1f27f152
      Alex Elder authored
      Add code for device tree support of clocks in the BCM281xx family of
      SoCs.  Machines in this family use peripheral clocks implemented by
      "Kona" clock control units (CCUs).  (Other Broadcom SoC families use
      Kona style CCUs as well, but support for them is not yet upstream.)
      A BCM281xx SoC has multiple CCUs, each of which manages a set of
      clocks on the SoC.  A Kona peripheral clock is composite clock that
      may include a gate, a parent clock multiplexor, and zero, one
      or two dividers.  There is a variety of gate types, and many gates
      implement hardware-managed gating (often called "auto-gating").
      Most dividers divide their input clock signal by an integer value
      (one or more).  There are also "fractional" dividers which allow
      division by non-integer values.  To accomodate such dividers,
      clock rates and dividers are generally maintained by the code in
      "scaled" form, which allows integer and fractional dividers to
      be handled in a uniform way.
      If present, the gate for a Kona peripheral clock must be enabled
      when a change is made to its multiplexor or one of its dividers.
      Additionally, dividers and multiplexors have trigger registers which
      must be used whenever the divider value or selected parent clock is
      changed.  The same trigger is often used for a divider and
      multiplexor, and a BCM281xx peripheral clock occasionally has two
      The gate, dividers, and parent clock selector are treated in this
      code as "components" of a peripheral clock.  Their functionality is
      implemented directly--e.g. the common clock framework gate
      implementation is not used for a Kona peripheral clock gate.  (This
      has being considered though, and the intention is to evolve this
      code to leverage common code as much as possible.)
      The source code is divided into three general portions:
              These implement the basic Kona clock functionality,
              including the clk_ops methods and various routines to
              manipulate registers and interpret their values.  This
              includes some functions used to set clocks to a desired
              initial state (though this feature is only partially
              implemented here).
              This contains generic run-time initialization code for
              data structures representing Kona CCUs and clocks.  This
              encapsulates the clock structure initialization that can't
              be done statically.  Note that there is a great deal of
              validity-checking code here, making explicit certain
              assumptions in the code.   This is mostly useful for adding
              new clock definitions and could possibly be disabled for
              production use.
              This file defines the specific CCUs used by BCM281XX family
              SoCs, as well as the specific clocks implemented by each.
              It declares a device tree clock match entry for each CCU
              This file defines the selector (index) values used to
              identify a particular clock provided by a CCU.  It consists
              entirely of C preprocessor constants, to be used by both the
              C source and device tree source files.
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Reviewed-by: default avatarTim Kryger <tim.kryger@linaro.org>
      Reviewed-by: default avatarMatt Porter <mporter@linaro.org>
      Acked-by: default avatarMike Turquette <mturquette@linaro.org>
      Signed-off-by: default avatarMatt Porter <mporter@linaro.org>
  34. 16 Jan, 2014 1 commit
  35. 28 Dec, 2013 1 commit