1. 14 Sep, 2018 1 commit
    • Linus Walleij's avatar
      pinctrl: Include <linux/gpio/driver.h> nothing else · 1c5fb66a
      Linus Walleij authored
      These drivers are GPIO drivers, and the do not need to use the
      legacy header in <linux/gpio.h>, go directly for
      <linux/gpio/driver.h> instead.
      
      Replace any use of GPIOF_* with 0/1, these flags are for
      consumers, not drivers.
      
      Get rid of a few gpio_to_irq() users that was littering
      around the place, use local callbacks or avoid using it at
      all.
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
      1c5fb66a
  2. 29 Aug, 2018 2 commits
    • Rob Herring's avatar
      pinctrl: Convert to using %pOFn instead of device_node.name · 94f4e54c
      Rob Herring authored
      In preparation to remove the node name pointer from struct device_node,
      convert printf users to use the %pOFn format specifier.
      
      Cc: Linus Walleij <linus.walleij@linaro.org>
      Cc: Dong Aisheng <aisheng.dong@nxp.com>
      Cc: Fabio Estevam <festevam@gmail.com>
      Cc: Shawn Guo <shawnguo@kernel.org>
      Cc: Stefan Agner <stefan@agner.ch>
      Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
      Cc: Sean Wang <sean.wang@mediatek.com>
      Cc: Matthias Brugger <matthias.bgg@gmail.com>
      Cc: Carlo Caione <carlo@caione.org>
      Cc: Kevin Hilman <khilman@baylibre.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Andrew Lunn <andrew@lunn.ch>
      Cc: Gregory Clement <gregory.clement@bootlin.com>
      Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
      Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
      Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
      Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
      Cc: Heiko Stuebner <heiko@sntech.de>
      Cc: Tony Lindgren <tony@atomide.com>
      Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
      Cc: Patrice Chotard <patrice.chotard@st.com>
      Cc: Barry Song <baohua@kernel.org>
      Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
      Cc: Alexandre Torgue <alexandre.torgue@st.com>
      Cc: Maxime Ripard <maxime.ripard@bootlin.com>
      Cc: Chen-Yu Tsai <wens@csie.org>
      Cc: linux-gpio@vger.kernel.org
      Cc: linux-mediatek@lists.infradead.org
      Cc: linux-arm-kernel@lists.infradead.org
      Cc: linux-amlogic@lists.infradead.org
      Cc: linux-rockchip@lists.infradead.org
      Cc: linux-omap@vger.kernel.org
      Acked-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
      Reviewed-by: default avatarAlexandre Belloni <alexandre.belloni@bootlin.com>
      Acked-by: default avatarTony Lindgren <tony@atomide.com>
      Acked-by: default avatarSean Wang <sean.wang@mediatek.com>
      Acked-by: Chen-Yu Tsai's avatarChen-Yu Tsai <wens@csie.org>
      Acked-by: Heiko Stuebner's avatarHeiko Stuebner <heiko@sntech.de>
      Signed-off-by: Rob Herring's avatarRob Herring <robh@kernel.org>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
      94f4e54c
    • Yixun Lan's avatar
      pinctrl: meson-g12a: add pinctrl driver support · 29ae0952
      Yixun Lan authored
      Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
      the previous Meson-AXG SoC, both use same pinmux ops (register layout).
      A new driver is needed here due to the differences in the pins.
      
      Starting from Meson-AXG SoC, the pinctrl controller block use 4
      continues register bits to specific the pin mux function, while comparing
      to old generation SoC which using variable length register bits for
      the pin mux definition. The new design greatly simplify the software model.
      
      For the detail example, one 32bit register can be divided into 8 parts,
      each has 4 bits whose value start from 0 - 7, each can describe one pin,
      the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
      the mux pin function.
      
      Please note, the GPIOE is actually located at AO (always on) bank.
      Acked-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Signed-off-by: default avatarXingyu Chen <xingyu.chen@amlogic.com>
      Signed-off-by: default avatarYixun Lan <yixun.lan@amlogic.com>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
      29ae0952
  3. 16 Jul, 2018 1 commit
  4. 16 May, 2018 2 commits
  5. 02 May, 2018 4 commits
  6. 02 Mar, 2018 1 commit
    • Martin Blumenstingl's avatar
      pinctrl: meson: meson8b: fix requesting GPIOs greater than GPIOZ_3 · 55af415b
      Martin Blumenstingl authored
      Meson8b is a cost reduced variant of the Meson8 SoC. It's package size
      is smaller than Meson8.
      Unfortunately there are a few key differences which cannot be seen
      without close inspection of the code and the public S805 datasheet:
      - the GPIOX bank is missing the GPIOX_12, GPIOX_13, GPIOX_14 and
        GPIOX_15 GPIOs
      - the GPIOY bank is missing the GPIOY_2, GPIOY_4, GPIOY_5, GPIOY_15 and
        GPIOY_16 GPIOs
      - the GPIODV bank is missing all GPIOs except GPIODV_9, GPIODV_24,
        GPIODV_25, GPIODV_26, GPIODV_27, GPIODV_28 and GPIODV_29
      - the GPIOZ bank is missing completely
      - there is a new GPIO bank called "DIF"
      
      This means that Meson8b only has 83 actual GPIO lines. Without any holes
      there would be 130 GPIO lines in total (120 are inherited from Meson8
      plus 10 new from the DIF bank).
      
      GPIOs greater GPIOZ_3 (whose ID is 83 - as a reminder: this is exactly
      the number of actual GPIO lines on Meson8b and also the value of
      meson8b_cbus_pinctrl_data.num_pins) cannot berequested. Using CARD_6
      (which used ID 100 prior to this patch, "base of the GPIO controller was
      382) as an example:
      $ echo 482 > /sys/class/gpio/export
      export_store: invalid GPIO 482
      
      This removes all non-existing pins from to dt-bindings header file
      (include/dt-bindings/gpio/meson8b-gpio.h). This allows us to have a
      consecutive numbering for the GPIO #defines (GPIOY_2 doesn't exist for
      example, so previously the GPIOY_3 ID was "GPIOY_1 + 2", after this
      patch it is "GPIOY_1 + 1"). As a nice side-effect this means that we get
      compile-time (instead of runtime) errors if Meson8b .dts uses a pin that
      only exists on Meson8.
      
      Additionally the pinctrl-meson8b driver has to be updated to handle this
      new GPIO numbering. By default a struct meson_bank only handles GPIO
      banks where the pins are numbered consecutively because it calculates
      the bit offsets based on the GPIO IDs.
      This is solved by  taking the original BANK() definition and splitting it
      into consecutive subsets (X0..11 and X16..21). The bit offsets for each
      new bank includes the skipped GPIOs (the definition of the "X0..11" bank
      is identical to the old "X" bank apart from the "last IRQ" field, the
      definition of the new, split "X16..21" bank takes the original "X" bank
      and adds 16 - the start of the new split bank - to the "first IRQ",
      pullen bit, pull bit, dir bit, out bit and in bit).
      
      Commit 984cffde ("pinctrl: Fix gpio/pin mapping for Meson8b")
      fixed the same issue by setting "ngpio" (of the gpio_chip) to 130.
      Unfortunately this broke in db80f0e1 ("pinctrl: meson: get rid of
      unneeded domain structures").
      The solution from this patch was considered to be better than the
      previous attempt at fixing this because it provides compile-time error
      checking for the GPIOs that exist on Meson8 but don't exist on Meson8b.
      
      The following pins were tested on an Odroid-C1 using the sysfs GPIO
      interface checking that their value (high or low) could be read:
      - GPIOX_0, GPIOX_1, GPIOX_2, GPIOX_3, GPIOX_4, GPIOX_5, GPIOX_6,
        GPIOX_7, GPIOX_8, GPIOX_9, GPIOX_10, GPIOX_11, GPIOX_18, GPIOX_19,
        GPIOX_20, GPIOX_21
      - GPIOY_3, GPIOY_7, GPIOY_8
      (some of these had to be pulled up because they were low by default,
      others were high by default so these had to be pulled down)
      Reported-by: default avatarLinus Lüssing <linus.luessing@c0d3.blue>
      Suggested-by: default avatarJerome Brunet <jbrunet@baylibre.com>
      Signed-off-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
      Reviewed-by: default avatarJerome Brunet <jbrunet@baylibre.com>
      Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
      55af415b
  7. 12 Feb, 2018 1 commit
  8. 12 Dec, 2017 1 commit
  9. 30 Nov, 2017 2 commits
  10. 16 Oct, 2017 2 commits
  11. 11 Oct, 2017 2 commits
  12. 06 Oct, 2017 1 commit
  13. 05 Oct, 2017 4 commits
  14. 22 Sep, 2017 1 commit
  15. 21 Sep, 2017 1 commit
  16. 16 Jun, 2017 1 commit
  17. 09 Jun, 2017 2 commits
  18. 29 May, 2017 9 commits
  19. 22 May, 2017 2 commits