Commit 6ac73095 authored by Beniamino Galvani's avatar Beniamino Galvani Committed by Linus Walleij

pinctrl: add driver for Amlogic Meson SoCs

This is a driver for the pinmux and GPIO controller available in
Amlogic Meson SoCs. It currently supports only Meson8, however the
common code should be generic enough to work also for other SoCs after
having defined the proper set of functions and groups.

GPIO interrupts are not supported at the moment due to lack of
documentation.
Signed-off-by: default avatarBeniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
parent 40b9e4fa
......@@ -96,6 +96,14 @@ config PINCTRL_FALCON
depends on SOC_FALCON
depends on PINCTRL_LANTIQ
config PINCTRL_MESON
bool
select PINMUX
select PINCONF
select GENERIC_PINCONF
select OF_GPIO
select REGMAP_MMIO
config PINCTRL_ROCKCHIP
bool
select PINMUX
......
......@@ -17,6 +17,7 @@ obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
obj-$(CONFIG_PINCTRL_MESON) += meson/
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
......
obj-y += pinctrl-meson8.o
obj-y += pinctrl-meson.o
This diff is collapsed.
/*
* Pin controller and GPIO driver for Amlogic Meson SoCs
*
* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/gpio.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/regmap.h>
#include <linux/types.h>
/**
* struct meson_pmx_group - a pinmux group
*
* @name: group name
* @pins: pins in the group
* @num_pins: number of pins in the group
* @is_gpio: whether the group is a single GPIO group
* @reg: register offset for the group in the domain mux registers
* @bit bit index enabling the group
* @domain: index of the domain this group belongs to
*/
struct meson_pmx_group {
const char *name;
const unsigned int *pins;
unsigned int num_pins;
bool is_gpio;
unsigned int reg;
unsigned int bit;
unsigned int domain;
};
/**
* struct meson_pmx_func - a pinmux function
*
* @name: function name
* @groups: groups in the function
* @num_groups: number of groups in the function
*/
struct meson_pmx_func {
const char *name;
const char * const *groups;
unsigned int num_groups;
};
/**
* struct meson_reg_desc - a register descriptor
*
* @reg: register offset in the regmap
* @bit: bit index in register
*
* The structure describes the information needed to control pull,
* pull-enable, direction, etc. for a single pin
*/
struct meson_reg_desc {
unsigned int reg;
unsigned int bit;
};
/**
* enum meson_reg_type - type of registers encoded in @meson_reg_desc
*/
enum meson_reg_type {
REG_PULLEN,
REG_PULL,
REG_DIR,
REG_OUT,
REG_IN,
NUM_REG,
};
/**
* struct meson bank
*
* @name: bank name
* @first: first pin of the bank
* @last: last pin of the bank
* @regs: array of register descriptors
*
* A bank represents a set of pins controlled by a contiguous set of
* bits in the domain registers. The structure specifies which bits in
* the regmap control the different functionalities. Each member of
* the @regs array refers to the first pin of the bank.
*/
struct meson_bank {
const char *name;
unsigned int first;
unsigned int last;
struct meson_reg_desc regs[NUM_REG];
};
/**
* struct meson_domain_data - domain platform data
*
* @name: name of the domain
* @banks: set of banks belonging to the domain
* @num_banks: number of banks in the domain
*/
struct meson_domain_data {
const char *name;
struct meson_bank *banks;
unsigned int num_banks;
unsigned int pin_base;
unsigned int num_pins;
};
/**
* struct meson_domain
*
* @reg_mux: registers for mux settings
* @reg_pullen: registers for pull-enable settings
* @reg_pull: registers for pull settings
* @reg_gpio: registers for gpio settings
* @chip: gpio chip associated with the domain
* @data; platform data for the domain
* @node: device tree node for the domain
*
* A domain represents a set of banks controlled by the same set of
* registers.
*/
struct meson_domain {
struct regmap *reg_mux;
struct regmap *reg_pullen;
struct regmap *reg_pull;
struct regmap *reg_gpio;
struct gpio_chip chip;
struct meson_domain_data *data;
struct device_node *of_node;
};
struct meson_pinctrl_data {
const struct pinctrl_pin_desc *pins;
struct meson_pmx_group *groups;
struct meson_pmx_func *funcs;
struct meson_domain_data *domain_data;
unsigned int num_pins;
unsigned int num_groups;
unsigned int num_funcs;
unsigned int num_domains;
};
struct meson_pinctrl {
struct device *dev;
struct pinctrl_dev *pcdev;
struct pinctrl_desc desc;
struct meson_pinctrl_data *data;
struct meson_domain *domains;
};
#define GROUP(grp, r, b) \
{ \
.name = #grp, \
.pins = grp ## _pins, \
.num_pins = ARRAY_SIZE(grp ## _pins), \
.reg = r, \
.bit = b, \
.domain = 0, \
}
#define GPIO_GROUP(gpio) \
{ \
.name = #gpio, \
.pins = (const unsigned int[]){ PIN_ ## gpio}, \
.num_pins = 1, \
.is_gpio = true, \
}
#define GROUP_AO(grp, r, b) \
{ \
.name = #grp, \
.pins = grp ## _pins, \
.num_pins = ARRAY_SIZE(grp ## _pins), \
.reg = r, \
.bit = b, \
.domain = 1, \
}
#define FUNCTION(fn) \
{ \
.name = #fn, \
.groups = fn ## _groups, \
.num_groups = ARRAY_SIZE(fn ## _groups), \
}
#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
{ \
.name = n, \
.first = f, \
.last = l, \
.regs = { \
[REG_PULLEN] = { per, peb }, \
[REG_PULL] = { pr, pb }, \
[REG_DIR] = { dr, db }, \
[REG_OUT] = { or, ob }, \
[REG_IN] = { ir, ib }, \
}, \
}
#define MESON_PIN(x) PINCTRL_PIN(PIN_ ## x, #x)
extern struct meson_pinctrl_data meson8_pinctrl_data;
This diff is collapsed.
/*
* GPIO definitions for Amlogic Meson8 SoCs
*
* Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef _DT_BINDINGS_MESON8_GPIO_H
#define _DT_BINDINGS_MESON8_GPIO_H
/* First GPIO chip */
#define GPIOX_0 0
#define GPIOX_1 1
#define GPIOX_2 2
#define GPIOX_3 3
#define GPIOX_4 4
#define GPIOX_5 5
#define GPIOX_6 6
#define GPIOX_7 7
#define GPIOX_8 8
#define GPIOX_9 9
#define GPIOX_10 10
#define GPIOX_11 11
#define GPIOX_12 12
#define GPIOX_13 13
#define GPIOX_14 14
#define GPIOX_15 15
#define GPIOX_16 16
#define GPIOX_17 17
#define GPIOX_18 18
#define GPIOX_19 19
#define GPIOX_20 20
#define GPIOX_21 21
#define GPIOY_0 22
#define GPIOY_1 23
#define GPIOY_2 24
#define GPIOY_3 25
#define GPIOY_4 26
#define GPIOY_5 27
#define GPIOY_6 28
#define GPIOY_7 29
#define GPIOY_8 30
#define GPIOY_9 31
#define GPIOY_10 32
#define GPIOY_11 33
#define GPIOY_12 34
#define GPIOY_13 35
#define GPIOY_14 36
#define GPIOY_15 37
#define GPIOY_16 38
#define GPIODV_0 39
#define GPIODV_1 40
#define GPIODV_2 41
#define GPIODV_3 42
#define GPIODV_4 43
#define GPIODV_5 44
#define GPIODV_6 45
#define GPIODV_7 46
#define GPIODV_8 47
#define GPIODV_9 48
#define GPIODV_10 49
#define GPIODV_11 50
#define GPIODV_12 51
#define GPIODV_13 52
#define GPIODV_14 53
#define GPIODV_15 54
#define GPIODV_16 55
#define GPIODV_17 56
#define GPIODV_18 57
#define GPIODV_19 58
#define GPIODV_20 59
#define GPIODV_21 60
#define GPIODV_22 61
#define GPIODV_23 62
#define GPIODV_24 63
#define GPIODV_25 64
#define GPIODV_26 65
#define GPIODV_27 66
#define GPIODV_28 67
#define GPIODV_29 68
#define GPIOH_0 69
#define GPIOH_1 70
#define GPIOH_2 71
#define GPIOH_3 72
#define GPIOH_4 73
#define GPIOH_5 74
#define GPIOH_6 75
#define GPIOH_7 76
#define GPIOH_8 77
#define GPIOH_9 78
#define GPIOZ_0 79
#define GPIOZ_1 80
#define GPIOZ_2 81
#define GPIOZ_3 82
#define GPIOZ_4 83
#define GPIOZ_5 84
#define GPIOZ_6 85
#define GPIOZ_7 86
#define GPIOZ_8 87
#define GPIOZ_9 88
#define GPIOZ_10 89
#define GPIOZ_11 90
#define GPIOZ_12 91
#define GPIOZ_13 92
#define GPIOZ_14 93
#define CARD_0 94
#define CARD_1 95
#define CARD_2 96
#define CARD_3 97
#define CARD_4 98
#define CARD_5 99
#define CARD_6 100
#define BOOT_0 101
#define BOOT_1 102
#define BOOT_2 103
#define BOOT_3 104
#define BOOT_4 105
#define BOOT_5 106
#define BOOT_6 107
#define BOOT_7 108
#define BOOT_8 109
#define BOOT_9 110
#define BOOT_10 111
#define BOOT_11 112
#define BOOT_12 113
#define BOOT_13 114
#define BOOT_14 115
#define BOOT_15 116
#define BOOT_16 117
#define BOOT_17 118
#define BOOT_18 119
/* Second GPIO chip */
#define GPIOAO_0 0
#define GPIOAO_1 1
#define GPIOAO_2 2
#define GPIOAO_3 3
#define GPIOAO_4 4
#define GPIOAO_5 5
#define GPIOAO_6 6
#define GPIOAO_7 7
#define GPIOAO_8 8
#define GPIOAO_9 9
#define GPIOAO_10 10
#define GPIOAO_11 11
#define GPIOAO_12 12
#define GPIOAO_13 13
#define GPIO_BSD_EN 14
#define GPIO_TEST_N 15
#endif /* _DT_BINDINGS_MESON8_GPIO_H */
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