Commit 598c6cfe authored by Dhinakaran Pandiyan's avatar Dhinakaran Pandiyan

drm/i915/psr: Enable PSR1 on gen-9+ HW

We have new tests and fixes in place since the feature was last
disabled. Try again for gen-9+ hardware and enable only PSR1 by default as
a first step.
v2: Remove typo fix and comment improvements (Rodrigo)

Cc: Jani Nikula <>
Cc: Jose Roberto de Souza <>
Cc: Paulo Zanoni <>
Cc: Rodrigo Vivi <>
Cc: Ville Syrjälä <>
References: commit 2ee7dc49 ("drm/i915: disable PSR by default on HSW/BDW")
References: commit dcb2e993 ("Revert "drm/i915: Enable PSR by default on Valleyview and Cherryview."")
Signed-off-by: Dhinakaran Pandiyan's avatarDhinakaran Pandiyan <>
Reviewed-by: default avatarRodrigo Vivi <>
Reviewed-by: José Roberto de Souza's avatarJosé Roberto de Souza <>
Tested-by: José Roberto de Souza's avatarJosé Roberto de Souza <>
parent 2ddcc982
......@@ -71,6 +71,10 @@ static bool psr_global_enabled(u32 debug)
static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state)
/* Disable PSR2 by default for all platforms */
if (i915_modparams.enable_psr == -1)
return false;
switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) {
return false;
......@@ -1066,12 +1070,9 @@ void intel_psr_init(struct drm_i915_private *dev_priv)
if (!dev_priv->psr.sink_support)
if (i915_modparams.enable_psr == -1) {
i915_modparams.enable_psr = dev_priv->vbt.psr.enable;
/* Per platform default: all disabled. */
i915_modparams.enable_psr = 0;
if (i915_modparams.enable_psr == -1)
if (INTEL_GEN(dev_priv) < 9 || !dev_priv->vbt.psr.enable)
i915_modparams.enable_psr = 0;
/* Set link_standby x link_off defaults */
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
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