• Matt Redfearn's avatar
    irqchip/mips-gic: Avoid spuriously handling masked interrupts · 285cb4f6
    Matt Redfearn authored
    Commit 7778c4b2 ("irqchip: mips-gic: Use pcpu_masks to avoid reading
    GIC_SH_MASK*") removed the read of the hardware mask register when
    handling shared interrupts, instead using the driver's shadow pcpu_masks
    entry as the effective mask. Unfortunately this did not take account of
    the write to pcpu_masks during gic_shared_irq_domain_map, which
    effectively unmasks the interrupt early. If an interrupt is asserted,
    gic_handle_shared_int decodes and processes the interrupt even though it
    has not yet been unmasked via gic_unmask_irq, which also sets the
    appropriate bit in pcpu_masks.
    On the MIPS Boston board, when a console command line of
    "console=ttyS0,115200n8r" is passed, the modem status IRQ is enabled in
    the UART, which is immediately raised to the GIC. The interrupt has been
    mapped, but no handler has yet been registered, nor is it expected to be
    unmasked. However, the write to pcpu_masks in gic_shared_irq_domain_map
    has effectively unmasked it, resulting in endless reports of:
    [    5.058454] irq 13, desc: ffffffff80a7ad80, depth: 1, count: 0, unhandled: 0
    [    5.062057] ->handle_irq():  ffffffff801b1838,
    [    5.062175] handle_bad_irq+0x0/0x2c0
    Where IRQ 13 is the UART interrupt.
    To fix this, just remove the write to pcpu_masks in
    gic_shared_irq_domain_map. The existing write in gic_unmask_irq is the
    correct place for what is now the effective unmasking.
    Cc: stable@vger.kernel.org
    Fixes: 7778c4b2 ("irqchip: mips-gic: Use pcpu_masks to avoid reading GIC_SH_MASK*")
    Signed-off-by: default avatarMatt Redfearn <matt.redfearn@mips.com>
    Reviewed-by: default avatarPaul Burton <paul.burton@mips.com>
    Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
irq-mips-gic.c 19.9 KB