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  • Reinette Chatre's avatar
    x86/intel_rdt: Use perf infrastructure for measurements · dd45407c
    Reinette Chatre authored
    
    
    The success of a cache pseudo-locked region is measured using
    performance monitoring events that are programmed directly at the time
    the user requests a measurement.
    
    Modifying the performance event registers directly is not appropriate
    since it circumvents the in-kernel perf infrastructure that exists to
    manage these resources and provide resource arbitration to the
    performance monitoring hardware.
    
    The cache pseudo-locking measurements are modified to use the in-kernel
    perf infrastructure. Performance events are created and validated with
    the appropriate perf API. The performance counters are still read as
    directly as possible to avoid the additional cache hits. This is
    done safely by first ensuring with the perf API that the counters have
    been programmed correctly and only accessing the counters in an
    interrupt disabled section where they are not able to be moved.
    
    As part of the transition to the in-kernel perf infrastructure the L2
    and L3 measurements are split into two separate measurements that can
    be triggered independently. This separation prevents additional cache
    misses incurred during the extra testing code used to decide if a
    L2 and/or L3 measurement should be made.
    
    Signed-off-by: default avatarReinette Chatre <reinette.chatre@intel.com>
    Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
    Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
    Cc: fenghua.yu@intel.com
    Cc: tony.luck@intel.com
    Cc: peterz@infradead.org
    Cc: acme@kernel.org
    Cc: gavin.hindman@intel.com
    Cc: jithu.joseph@intel.com
    Cc: dave.hansen@intel.com
    Cc: hpa@zytor.com
    Link: https://lkml.kernel.org/r/fc24e728b446404f42c78573c506e98cd0599873.1537468643.git.reinette.chatre@intel.com
    dd45407c