• Agustin Vega-Frias's avatar
    perf: qcom: Add L3 cache PMU driver · 3071f13d
    Agustin Vega-Frias authored
    This adds a new dynamic PMU to the Perf Events framework to program
    and control the L3 cache PMUs in some Qualcomm Technologies SOCs.
    The driver supports a distributed cache architecture where the overall
    cache for a socket is comprised of multiple slices each with its own PMU.
    Access to each individual PMU is provided even though all CPUs share all
    the slices. User space needs to aggregate to individual counts to provide
    a global picture.
    The driver exports formatting and event information to sysfs so it can
    be used by the perf user space tools with the syntaxes:
       perf stat -a -e l3cache_0_0/read-miss/
       perf stat -a -e l3cache_0_0/event=0x21/
    Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
    Signed-off-by: default avatarAgustin Vega-Frias <agustinv@codeaurora.org>
    [will: fixed sparse issues]
    Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
qcom_l3_pmu.txt 1.31 KB