• Daniel Kurtz's avatar
    pinctrl/amd: poll InterruptEnable bits in enable_irq · 4c1de041
    Daniel Kurtz authored
    In certain cases interrupt enablement will be delayed relative to when
    the InterruptEnable bits are written.  One example of this is when
    a GPIO's "debounce" logice is first enabled.  After enabling debounce,
    there is a 900 us "warm up" period during which InterruptEnable[0]
    (bit 11) will read as 0 despite being written 1.  During this time
    InterruptSts will not be updated, nor will interrupts be delivered, even
    if the GPIO's interrupt configuration has been written to the register.
    
    To work around this delay, poll the InterruptEnable bits after setting
    them to ensure interrupts have truly been enabled in hardware before
    returning from the irq_enable handler.
    Signed-off-by: default avatarDaniel Kurtz <djkurtz@chromium.org>
    Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
    4c1de041
pinctrl-amd.c 25.2 KB