• Linus Torvalds's avatar
    Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux · db06f826
    Linus Torvalds authored
    Pull clk updates from Stephen Boyd:
     "The new and exciting feature this time around is in the clk core.
      We've added duty cycle support to the clk API so that clk signal duty
      cycle ratios can be adjusted while taking into account things like clk
      dividers and clk tree hierarchy. So far only one SoC has implemented
      support for this, but I expect there will be more to come in the
      Outside of the core, we have the usual pile of clk driver updates and
      additions. The Amlogic meson driver got the most lines in the diffstat
      this time around because it added support for a whole bunch of
      hardware and duty cycle configuration. After that the Rockchip PX30,
      Qualcomm SDM845, and Renesas SoC drivers fill in a majority of the
      diff. We're left with the collection of non-critical fixes after that.
      Overall it looks pretty quiet this time.
       - Clk duty cycle support
       - Proper CLK_SET_RATE_GATE support throughout the tree
      New Drivers:
       - Actions Semi Owl series S700 SoC clk driver
       - Qualcomm SDM845 display clock controller
       - i.MX6SX ocram_s clk support
       - Uniphier NAND, USB3 PHY, and SPI clk support
       - Qualcomm RPMh clk driver
       - i.MX7D mailbox clk support
       - Maxim 9485 Programmable Clock Generator
       - expose 32 kHz PLL on PXA SoCs
       - imx6sll GPIO clk gate support
       - Atmel at91 I2S audio clk support
       - SI544/SI514 clk on/off support
       - i.MX6UL GPIO clock gates in CCM CCGR
       - Renesas Crypto Engine clocks on R-Car H3
       - Renesas clk support for the new RZ/N1D SoC
       - Allwinner A64 display engine clock support
       - support for Rockchip's PX30 SoC
       - Amlogic Meson axg PCIe and audio clocks
       - Amlogic Meson GEN CLK on gxbb, gxl and axg
       - remove an unused variable from Exynos4412 ISP driver
       - fix a thinko bug in SCMI clk division logic
       - add missing of_node_put()s in some i.MX clk drivers
       - Tegra SDMMC clk jitter improvements with high speed signaling modes
       - SPDX tagging for qcom and cs2000-cp drivers
       - stop leaking con ids in __clk_put()
       - fix a corner case in fixed factor clk probing where node is in DT
         but parent clk is registered much later
       - Marvell Armada 3700 clk_pm_cpu_get_parent() had an invalid return
       - i.MX clk init arrays removed in place of CLK_IS_CRITICAL
       - convert to CLK_IS_CRITICAL for i.MX51/53 driver
       - fix Tegra BPMP driver oops when xlating a NULL clk
       - proper default configuration for vic03 and vde clks on Tegra124
       - mark Tegra memory controller clks as critical
       - fix array bounds clamp in Tegra's emc determine_rate() op
       - Ingenic i2s bit update and allow UDC clk to gate
       - fix name of aspeed SDC clk define to have only one 'CLK'
       - fix i.MX6QDL video clk parent
       - critical clk markings for qcom SDM845
       - fix Stratix10 mpu_free_clk and sdmmc_free_clk parents
       - mark Rockchip's pclk_rkpwm_pmu as critical clock, due to it
         supplying the pwm used to drive the logic supply of the rk3399
    * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (85 commits)
      clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399
      clk: cs2000-cp: convert to SPDX identifiers
      clk: scmi: Fix the rounding of clock rate
      clk: qcom: Add display clock controller driver for SDM845
      clk: mvebu: armada-37xx-periph: Remove unused var num_parents
      clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable
      clk: actions: Add S700 SoC clock support
      dt-bindings: clock: Add S700 support for Actions Semi Soc's
      clk: actions: Add missing REGMAP_MMIO dependency
      clk: uniphier: add clock frequency support for SPI
      clk: uniphier: add more USB3 PHY clocks
      clk: uniphier: add NAND 200MHz clock
      clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks
      clk: tegra: Add sdmmc mux divider clock
      clk: tegra: Refactor fractional divider calculation
      clk: tegra: Fix includes required by fence_udelay()
      clk: imx6sll: fix missing of_node_put()
      clk: imx6ul: fix missing of_node_put()
      clk: imx: add ocram_s clock for i.mx6sx
      clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent
clk-aspeed.c 20 KB