• Yixun Lan's avatar
    pinctrl: meson-g12a: add pinctrl driver support · 29ae0952
    Yixun Lan authored
    Add the pinctrl driver for Meson-G12A SoC which share the similar IP as
    the previous Meson-AXG SoC, both use same pinmux ops (register layout).
    A new driver is needed here due to the differences in the pins.
    
    Starting from Meson-AXG SoC, the pinctrl controller block use 4
    continues register bits to specific the pin mux function, while comparing
    to old generation SoC which using variable length register bits for
    the pin mux definition. The new design greatly simplify the software model.
    
    For the detail example, one 32bit register can be divided into 8 parts,
    each has 4 bits whose value start from 0 - 7, each can describe one pin,
    the value 0 is always devoted to GPIO function, while 1 - 7 devoted to
    the mux pin function.
    
    Please note, the GPIOE is actually located at AO (always on) bank.
    Acked-by: default avatarMartin Blumenstingl <martin.blumenstingl@googlemail.com>
    Signed-off-by: default avatarXingyu Chen <xingyu.chen@amlogic.com>
    Signed-off-by: default avatarYixun Lan <yixun.lan@amlogic.com>
    Signed-off-by: Linus Walleij's avatarLinus Walleij <linus.walleij@linaro.org>
    29ae0952
Makefile 491 Bytes