mce_amd.c 24.6 KB
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#include <linux/module.h>
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#include <linux/slab.h>

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#include <asm/cpu.h>

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#include "mce_amd.h"
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static struct amd_decoder_ops *fam_ops;

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static u8 xec_mask	 = 0xf;
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static bool report_gart_errors;
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static void (*decode_dram_ecc)(int node_id, struct mce *m);
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void amd_report_gart_errors(bool v)
{
	report_gart_errors = v;
}
EXPORT_SYMBOL_GPL(amd_report_gart_errors);

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void amd_register_ecc_decoder(void (*f)(int, struct mce *))
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{
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	decode_dram_ecc = f;
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}
EXPORT_SYMBOL_GPL(amd_register_ecc_decoder);

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void amd_unregister_ecc_decoder(void (*f)(int, struct mce *))
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{
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	if (decode_dram_ecc) {
		WARN_ON(decode_dram_ecc != f);
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		decode_dram_ecc = NULL;
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	}
}
EXPORT_SYMBOL_GPL(amd_unregister_ecc_decoder);

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/*
 * string representation for the different MCA reported error types, see F3x48
 * or MSR0000_0411.
 */
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/* transaction type */
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static const char * const tt_msgs[] = { "INSN", "DATA", "GEN", "RESV" };
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/* cache level */
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static const char * const ll_msgs[] = { "RESV", "L1", "L2", "L3/GEN" };
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/* memory transaction type */
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static const char * const rrrr_msgs[] = {
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       "GEN", "RD", "WR", "DRD", "DWR", "IRD", "PRF", "EV", "SNP"
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};

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/* participating processor */
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const char * const pp_msgs[] = { "SRC", "RES", "OBS", "GEN" };
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EXPORT_SYMBOL_GPL(pp_msgs);
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/* request timeout */
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static const char * const to_msgs[] = { "no timeout", "timed out" };
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/* memory or i/o */
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static const char * const ii_msgs[] = { "MEM", "RESV", "IO", "GEN" };
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/* internal error type */
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static const char * const uu_msgs[] = { "RESV", "RESV", "HWA", "RESV" };
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static const char * const f15h_mc1_mce_desc[] = {
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	"UC during a demand linefill from L2",
	"Parity error during data load from IC",
	"Parity error for IC valid bit",
	"Main tag parity error",
	"Parity error in prediction queue",
	"PFB data/address parity error",
	"Parity error in the branch status reg",
	"PFB promotion address error",
	"Tag error during probe/victimization",
	"Parity error for IC probe tag valid bit",
	"PFB non-cacheable bit parity error",
	"PFB valid bit parity error",			/* xec = 0xd */
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	"Microcode Patch Buffer",			/* xec = 010 */
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	"uop queue",
	"insn buffer",
	"predecode buffer",
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	"fetch address FIFO",
	"dispatch uop queue"
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};

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static const char * const f15h_mc2_mce_desc[] = {
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	"Fill ECC error on data fills",			/* xec = 0x4 */
	"Fill parity error on insn fills",
	"Prefetcher request FIFO parity error",
	"PRQ address parity error",
	"PRQ data parity error",
	"WCC Tag ECC error",
	"WCC Data ECC error",
	"WCB Data parity error",
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	"VB Data ECC or parity error",
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	"L2 Tag ECC error",				/* xec = 0x10 */
	"Hard L2 Tag ECC error",
	"Multiple hits on L2 tag",
	"XAB parity error",
	"PRB address parity error"
};

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static const char * const mc4_mce_desc[] = {
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	"DRAM ECC error detected on the NB",
	"CRC error detected on HT link",
	"Link-defined sync error packets detected on HT link",
	"HT Master abort",
	"HT Target abort",
	"Invalid GART PTE entry during GART table walk",
	"Unsupported atomic RMW received from an IO link",
	"Watchdog timeout due to lack of progress",
	"DRAM ECC error detected on the NB",
	"SVM DMA Exclusion Vector error",
	"HT data error detected on link",
	"Protocol error (link, L3, probe filter)",
	"NB internal arrays parity error",
	"DRAM addr/ctl signals parity error",
	"IO link transmission error",
	"L3 data cache ECC error",			/* xec = 0x1c */
	"L3 cache tag error",
	"L3 LRU parity bits error",
	"ECC Error in the Probe Filter directory"
};

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static const char * const mc5_mce_desc[] = {
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	"CPU Watchdog timer expire",
	"Wakeup array dest tag",
	"AG payload array",
	"EX payload array",
	"IDRF array",
	"Retire dispatch queue",
	"Mapper checkpoint array",
	"Physical register file EX0 port",
	"Physical register file EX1 port",
	"Physical register file AG0 port",
	"Physical register file AG1 port",
	"Flag register file",
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	"DE error occurred",
	"Retire status queue"
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};

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static const char * const mc6_mce_desc[] = {
	"Hardware Assertion",
	"Free List",
	"Physical Register File",
	"Retire Queue",
	"Scheduler table",
	"Status Register File",
};

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/* Scalable MCA error strings */
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static const char * const smca_ls_mce_desc[] = {
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	"Load queue parity",
	"Store queue parity",
	"Miss address buffer payload parity",
	"L1 TLB parity",
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	"Reserved",
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	"DC tag error type 6",
	"DC tag error type 1",
	"Internal error type 1",
	"Internal error type 2",
	"Sys Read data error thread 0",
	"Sys read data error thread 1",
	"DC tag error type 2",
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	"DC data error type 1 (poison consumption)",
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	"DC data error type 2",
	"DC data error type 3",
	"DC tag error type 4",
	"L2 TLB parity",
	"PDC parity error",
	"DC tag error type 3",
	"DC tag error type 5",
	"L2 fill data error",
};

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static const char * const smca_if_mce_desc[] = {
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	"microtag probe port parity error",
	"IC microtag or full tag multi-hit error",
	"IC full tag parity",
	"IC data array parity",
	"Decoupling queue phys addr parity error",
	"L0 ITLB parity error",
	"L1 ITLB parity error",
	"L2 ITLB parity error",
	"BPQ snoop parity on Thread 0",
	"BPQ snoop parity on Thread 1",
	"L1 BTB multi-match error",
	"L2 BTB multi-match error",
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	"L2 Cache Response Poison error",
	"System Read Data error",
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};

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static const char * const smca_l2_mce_desc[] = {
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	"L2M tag multi-way-hit error",
	"L2M tag ECC error",
	"L2M data ECC error",
	"HW assert",
};

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static const char * const smca_de_mce_desc[] = {
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	"uop cache tag parity error",
	"uop cache data parity error",
	"Insn buffer parity error",
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	"uop queue parity error",
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	"Insn dispatch queue parity error",
	"Fetch address FIFO parity",
	"Patch RAM data parity",
	"Patch RAM sequencer parity",
	"uop buffer parity"
};

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static const char * const smca_ex_mce_desc[] = {
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	"Watchdog timeout error",
	"Phy register file parity",
	"Flag register file parity",
	"Immediate displacement register file parity",
	"Address generator payload parity",
	"EX payload parity",
	"Checkpoint queue parity",
	"Retire dispatch queue parity",
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	"Retire status queue parity error",
	"Scheduling queue parity error",
	"Branch buffer queue parity error",
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};

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static const char * const smca_fp_mce_desc[] = {
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	"Physical register file parity",
	"Freelist parity error",
	"Schedule queue parity",
	"NSQ parity error",
	"Retire queue parity",
	"Status register file parity",
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	"Hardware assertion",
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};

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static const char * const smca_l3_mce_desc[] = {
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	"Shadow tag macro ECC error",
	"Shadow tag macro multi-way-hit error",
	"L3M tag ECC error",
	"L3M tag multi-way-hit error",
	"L3M data ECC error",
	"XI parity, L3 fill done channel error",
	"L3 victim queue parity",
	"L3 HW assert",
};

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static const char * const smca_cs_mce_desc[] = {
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	"Illegal request from transport layer",
	"Address violation",
	"Security violation",
	"Illegal response from transport layer",
	"Unexpected response",
	"Parity error on incoming request or probe response data",
	"Parity error on incoming read response data",
	"Atomic request parity",
	"ECC error on probe filter access",
};

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static const char * const smca_pie_mce_desc[] = {
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	"HW assert",
	"Internal PIE register security violation",
	"Error on GMI link",
	"Poison data written to internal PIE register",
};

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static const char * const smca_umc_mce_desc[] = {
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	"DRAM ECC error",
	"Data poison error on DRAM",
	"SDP parity error",
	"Advanced peripheral bus error",
	"Command/address parity error",
	"Write data CRC error",
};

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static const char * const smca_pb_mce_desc[] = {
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	"Parameter Block RAM ECC error",
};

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static const char * const smca_psp_mce_desc[] = {
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	"PSP RAM ECC or parity error",
};

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static const char * const smca_smu_mce_desc[] = {
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	"SMU RAM ECC or parity error",
};

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struct smca_mce_desc {
	const char * const *descs;
	unsigned int num_descs;
};

static struct smca_mce_desc smca_mce_descs[] = {
	[SMCA_LS]	= { smca_ls_mce_desc,	ARRAY_SIZE(smca_ls_mce_desc)	},
	[SMCA_IF]	= { smca_if_mce_desc,	ARRAY_SIZE(smca_if_mce_desc)	},
	[SMCA_L2_CACHE]	= { smca_l2_mce_desc,	ARRAY_SIZE(smca_l2_mce_desc)	},
	[SMCA_DE]	= { smca_de_mce_desc,	ARRAY_SIZE(smca_de_mce_desc)	},
	[SMCA_EX]	= { smca_ex_mce_desc,	ARRAY_SIZE(smca_ex_mce_desc)	},
	[SMCA_FP]	= { smca_fp_mce_desc,	ARRAY_SIZE(smca_fp_mce_desc)	},
	[SMCA_L3_CACHE]	= { smca_l3_mce_desc,	ARRAY_SIZE(smca_l3_mce_desc)	},
	[SMCA_CS]	= { smca_cs_mce_desc,	ARRAY_SIZE(smca_cs_mce_desc)	},
	[SMCA_PIE]	= { smca_pie_mce_desc,	ARRAY_SIZE(smca_pie_mce_desc)	},
	[SMCA_UMC]	= { smca_umc_mce_desc,	ARRAY_SIZE(smca_umc_mce_desc)	},
	[SMCA_PB]	= { smca_pb_mce_desc,	ARRAY_SIZE(smca_pb_mce_desc)	},
	[SMCA_PSP]	= { smca_psp_mce_desc,	ARRAY_SIZE(smca_psp_mce_desc)	},
	[SMCA_SMU]	= { smca_smu_mce_desc,	ARRAY_SIZE(smca_smu_mce_desc)	},
};

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static bool f12h_mc0_mce(u16 ec, u8 xec)
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{
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	bool ret = false;
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	if (MEM_ERROR(ec)) {
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		u8 ll = LL(ec);
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		ret = true;
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		if (ll == LL_L2)
			pr_cont("during L1 linefill from L2.\n");
		else if (ll == LL_L1)
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			pr_cont("Data/Tag %s error.\n", R4_MSG(ec));
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		else
			ret = false;
	}
	return ret;
}
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static bool f10h_mc0_mce(u16 ec, u8 xec)
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{
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	if (R4(ec) == R4_GEN && LL(ec) == LL_L1) {
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		pr_cont("during data scrub.\n");
		return true;
	}
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	return f12h_mc0_mce(ec, xec);
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}

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static bool k8_mc0_mce(u16 ec, u8 xec)
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{
	if (BUS_ERROR(ec)) {
		pr_cont("during system linefill.\n");
		return true;
	}
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	return f10h_mc0_mce(ec, xec);
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}

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static bool cat_mc0_mce(u16 ec, u8 xec)
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{
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	u8 r4	 = R4(ec);
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	bool ret = true;

	if (MEM_ERROR(ec)) {

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		if (TT(ec) != TT_DATA || LL(ec) != LL_L1)
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			return false;

		switch (r4) {
		case R4_DRD:
		case R4_DWR:
			pr_cont("Data/Tag parity error due to %s.\n",
				(r4 == R4_DRD ? "load/hw prf" : "store"));
			break;
		case R4_EVICT:
			pr_cont("Copyback parity error on a tag miss.\n");
			break;
		case R4_SNOOP:
			pr_cont("Tag parity error during snoop.\n");
			break;
		default:
			ret = false;
		}
	} else if (BUS_ERROR(ec)) {

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		if ((II(ec) != II_MEM && II(ec) != II_IO) || LL(ec) != LL_LG)
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			return false;

		pr_cont("System read data error on a ");

		switch (r4) {
		case R4_RD:
			pr_cont("TLB reload.\n");
			break;
		case R4_DWR:
			pr_cont("store.\n");
			break;
		case R4_DRD:
			pr_cont("load.\n");
			break;
		default:
			ret = false;
		}
	} else {
		ret = false;
	}

	return ret;
}

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static bool f15h_mc0_mce(u16 ec, u8 xec)
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{
	bool ret = true;

	if (MEM_ERROR(ec)) {

		switch (xec) {
		case 0x0:
			pr_cont("Data Array access error.\n");
			break;

		case 0x1:
			pr_cont("UC error during a linefill from L2/NB.\n");
			break;

		case 0x2:
		case 0x11:
			pr_cont("STQ access error.\n");
			break;

		case 0x3:
			pr_cont("SCB access error.\n");
			break;

		case 0x10:
			pr_cont("Tag error.\n");
			break;

		case 0x12:
			pr_cont("LDQ access error.\n");
			break;

		default:
			ret = false;
		}
	} else if (BUS_ERROR(ec)) {

		if (!xec)
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			pr_cont("System Read Data Error.\n");
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		else
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			pr_cont(" Internal error condition type %d.\n", xec);
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	} else if (INT_ERROR(ec)) {
		if (xec <= 0x1f)
			pr_cont("Hardware Assert.\n");
		else
			ret = false;

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	} else
		ret = false;

	return ret;
}

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static void decode_mc0_mce(struct mce *m)
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{
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	u16 ec = EC(m->status);
	u8 xec = XEC(m->status, xec_mask);
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	pr_emerg(HW_ERR "MC0 Error: ");
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	/* TLB error signatures are the same across families */
	if (TLB_ERROR(ec)) {
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		if (TT(ec) == TT_DATA) {
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			pr_cont("%s TLB %s.\n", LL_MSG(ec),
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				((xec == 2) ? "locked miss"
					    : (xec ? "multimatch" : "parity")));
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			return;
		}
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	} else if (fam_ops->mc0_mce(ec, xec))
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		;
	else
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		pr_emerg(HW_ERR "Corrupted MC0 MCE info?\n");
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}

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static bool k8_mc1_mce(u16 ec, u8 xec)
473
{
474
	u8 ll	 = LL(ec);
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	bool ret = true;
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	if (!MEM_ERROR(ec))
		return false;
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	if (ll == 0x2)
		pr_cont("during a linefill from L2.\n");
	else if (ll == 0x1) {
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		switch (R4(ec)) {
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		case R4_IRD:
			pr_cont("Parity error during data load.\n");
			break;
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		case R4_EVICT:
			pr_cont("Copyback Parity/Victim error.\n");
			break;

		case R4_SNOOP:
			pr_cont("Tag Snoop error.\n");
			break;

		default:
			ret = false;
			break;
		}
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	} else
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		ret = false;
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	return ret;
}

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static bool cat_mc1_mce(u16 ec, u8 xec)
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{
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	u8 r4    = R4(ec);
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	bool ret = true;
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	if (!MEM_ERROR(ec))
		return false;

	if (TT(ec) != TT_INSTR)
		return false;

	if (r4 == R4_IRD)
		pr_cont("Data/tag array parity error for a tag hit.\n");
	else if (r4 == R4_SNOOP)
		pr_cont("Tag error during snoop/victimization.\n");
	else if (xec == 0x0)
		pr_cont("Tag parity error from victim castout.\n");
	else if (xec == 0x2)
		pr_cont("Microcode patch RAM parity error.\n");
	else
		ret = false;
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	return ret;
}

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static bool f15h_mc1_mce(u16 ec, u8 xec)
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{
	bool ret = true;

	if (!MEM_ERROR(ec))
		return false;

	switch (xec) {
	case 0x0 ... 0xa:
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		pr_cont("%s.\n", f15h_mc1_mce_desc[xec]);
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		break;

	case 0xd:
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		pr_cont("%s.\n", f15h_mc1_mce_desc[xec-2]);
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		break;

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	case 0x10:
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		pr_cont("%s.\n", f15h_mc1_mce_desc[xec-4]);
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		break;

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	case 0x11 ... 0x15:
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		pr_cont("Decoder %s parity error.\n", f15h_mc1_mce_desc[xec-4]);
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		break;

	default:
		ret = false;
	}
	return ret;
}

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static void decode_mc1_mce(struct mce *m)
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{
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	u16 ec = EC(m->status);
	u8 xec = XEC(m->status, xec_mask);
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	pr_emerg(HW_ERR "MC1 Error: ");
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	if (TLB_ERROR(ec))
		pr_cont("%s TLB %s.\n", LL_MSG(ec),
			(xec ? "multimatch" : "parity error"));
	else if (BUS_ERROR(ec)) {
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		bool k8 = (boot_cpu_data.x86 == 0xf && (m->status & BIT_64(58)));
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		pr_cont("during %s.\n", (k8 ? "system linefill" : "NB data read"));
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	} else if (INT_ERROR(ec)) {
		if (xec <= 0x3f)
			pr_cont("Hardware Assert.\n");
		else
			goto wrong_mc1_mce;
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	} else if (fam_ops->mc1_mce(ec, xec))
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		;
	else
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		goto wrong_mc1_mce;

	return;

wrong_mc1_mce:
	pr_emerg(HW_ERR "Corrupted MC1 MCE info?\n");
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}

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static bool k8_mc2_mce(u16 ec, u8 xec)
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{
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	bool ret = true;
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	if (xec == 0x1)
		pr_cont(" in the write data buffers.\n");
	else if (xec == 0x3)
		pr_cont(" in the victim data buffers.\n");
	else if (xec == 0x2 && MEM_ERROR(ec))
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		pr_cont(": %s error in the L2 cache tags.\n", R4_MSG(ec));
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	else if (xec == 0x0) {
		if (TLB_ERROR(ec))
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			pr_cont("%s error in a Page Descriptor Cache or Guest TLB.\n",
				TT_MSG(ec));
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		else if (BUS_ERROR(ec))
			pr_cont(": %s/ECC error in data read from NB: %s.\n",
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				R4_MSG(ec), PP_MSG(ec));
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		else if (MEM_ERROR(ec)) {
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			u8 r4 = R4(ec);
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			if (r4 >= 0x7)
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				pr_cont(": %s error during data copyback.\n",
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					R4_MSG(ec));
			else if (r4 <= 0x1)
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				pr_cont(": %s parity/ECC error during data "
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					"access from L2.\n", R4_MSG(ec));
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			else
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				ret = false;
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		} else
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			ret = false;
621
	} else
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		ret = false;
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624
	return ret;
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}

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static bool f15h_mc2_mce(u16 ec, u8 xec)
628
{
629
	bool ret = true;
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	if (TLB_ERROR(ec)) {
		if (xec == 0x0)
			pr_cont("Data parity TLB read error.\n");
		else if (xec == 0x1)
			pr_cont("Poison data provided for TLB fill.\n");
		else
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			ret = false;
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	} else if (BUS_ERROR(ec)) {
		if (xec > 2)
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			ret = false;
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		pr_cont("Error during attempted NB data read.\n");
	} else if (MEM_ERROR(ec)) {
		switch (xec) {
		case 0x4 ... 0xc:
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			pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x4]);
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			break;

		case 0x10 ... 0x14:
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			pr_cont("%s.\n", f15h_mc2_mce_desc[xec - 0x7]);
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			break;

		default:
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			ret = false;
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		}
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	} else if (INT_ERROR(ec)) {
		if (xec <= 0x3f)
			pr_cont("Hardware Assert.\n");
		else
			ret = false;
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	}

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	return ret;
}

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static bool f16h_mc2_mce(u16 ec, u8 xec)
{
	u8 r4 = R4(ec);

	if (!MEM_ERROR(ec))
		return false;

	switch (xec) {
	case 0x04 ... 0x05:
		pr_cont("%cBUFF parity error.\n", (r4 == R4_RD) ? 'I' : 'O');
		break;

	case 0x09 ... 0x0b:
	case 0x0d ... 0x0f:
		pr_cont("ECC error in L2 tag (%s).\n",
			((r4 == R4_GEN)   ? "BankReq" :
			((r4 == R4_SNOOP) ? "Prb"     : "Fill")));
		break;

	case 0x10 ... 0x19:
	case 0x1b:
		pr_cont("ECC error in L2 data array (%s).\n",
			(((r4 == R4_RD) && !(xec & 0x3)) ? "Hit"  :
			((r4 == R4_GEN)   ? "Attr" :
			((r4 == R4_EVICT) ? "Vict" : "Fill"))));
		break;

	case 0x1c ... 0x1d:
	case 0x1f:
		pr_cont("Parity error in L2 attribute bits (%s).\n",
			((r4 == R4_RD)  ? "Hit"  :
			((r4 == R4_GEN) ? "Attr" : "Fill")));
		break;

	default:
		return false;
	}

	return true;
}

707 708 709 710
static void decode_mc2_mce(struct mce *m)
{
	u16 ec = EC(m->status);
	u8 xec = XEC(m->status, xec_mask);
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712 713 714 715
	pr_emerg(HW_ERR "MC2 Error: ");

	if (!fam_ops->mc2_mce(ec, xec))
		pr_cont(HW_ERR "Corrupted MC2 MCE info?\n");
716 717
}

718
static void decode_mc3_mce(struct mce *m)
719
{
720 721
	u16 ec = EC(m->status);
	u8 xec = XEC(m->status, xec_mask);
722

723
	if (boot_cpu_data.x86 >= 0x14) {
724
		pr_emerg("You shouldn't be seeing MC3 MCE on this cpu family,"
725 726 727
			 " please report on LKML.\n");
		return;
	}
728

729
	pr_emerg(HW_ERR "MC3 Error");
730 731

	if (xec == 0x0) {
732
		u8 r4 = R4(ec);
733

734
		if (!BUS_ERROR(ec) || (r4 != R4_DRD && r4 != R4_DWR))
735
			goto wrong_mc3_mce;
736

737
		pr_cont(" during %s.\n", R4_MSG(ec));
738
	} else
739
		goto wrong_mc3_mce;
740

741 742
	return;

743 744
 wrong_mc3_mce:
	pr_emerg(HW_ERR "Corrupted MC3 MCE info?\n");
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}

747
static void decode_mc4_mce(struct mce *m)
748
{
749
	unsigned int fam = x86_family(m->cpuid);
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	int node_id = amd_get_nb_id(m->extcpu);
	u16 ec = EC(m->status);
	u8 xec = XEC(m->status, 0x1f);
	u8 offset = 0;
754

755
	pr_emerg(HW_ERR "MC4 Error (node %d): ", node_id);
756

757 758
	switch (xec) {
	case 0x0 ... 0xe:
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		/* special handling for DRAM ECCs */
		if (xec == 0x0 || xec == 0x8) {
			/* no ECCs on F11h */
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			if (fam == 0x11)
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				goto wrong_mc4_mce;
765

766
			pr_cont("%s.\n", mc4_mce_desc[xec]);
767

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			if (decode_dram_ecc)
				decode_dram_ecc(node_id, m);
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			return;
		}
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		break;

	case 0xf:
		if (TLB_ERROR(ec))
			pr_cont("GART Table Walk data error.\n");
		else if (BUS_ERROR(ec))
			pr_cont("DMA Exclusion Vector Table Walk error.\n");
		else
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			goto wrong_mc4_mce;
781
		return;
782

783
	case 0x19:
784
		if (fam == 0x15 || fam == 0x16)
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			pr_cont("Compute Unit Data Error.\n");
		else
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			goto wrong_mc4_mce;
788
		return;
789

790
	case 0x1c ... 0x1f:
791
		offset = 13;
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		break;

	default:
795
		goto wrong_mc4_mce;
796
	}
797

798
	pr_cont("%s.\n", mc4_mce_desc[xec - offset]);
799 800
	return;

801 802
 wrong_mc4_mce:
	pr_emerg(HW_ERR "Corrupted MC4 MCE info?\n");
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}

805
static void decode_mc5_mce(struct mce *m)
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806
{
807
	unsigned int fam = x86_family(m->cpuid);
808
	u16 ec = EC(m->status);
809
	u8 xec = XEC(m->status, xec_mask);
810

811
	if (fam == 0xf || fam == 0x11)
812
		goto wrong_mc5_mce;
813

814
	pr_emerg(HW_ERR "MC5 Error: ");
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	if (INT_ERROR(ec)) {
		if (xec <= 0x1f) {
			pr_cont("Hardware Assert.\n");
			return;
		} else
			goto wrong_mc5_mce;
	}

824
	if (xec == 0x0 || xec == 0xc)
825
		pr_cont("%s.\n", mc5_mce_desc[xec]);
826
	else if (xec <= 0xd)
827
		pr_cont("%s parity error.\n", mc5_mce_desc[xec]);
828
	else
829
		goto wrong_mc5_mce;
830 831

	return;
832

833 834
 wrong_mc5_mce:
	pr_emerg(HW_ERR "Corrupted MC5 MCE info?\n");
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}

837
static void decode_mc6_mce(struct mce *m)
838
{
839
	u8 xec = XEC(m->status, xec_mask);
840

841
	pr_emerg(HW_ERR "MC6 Error: ");
842

843
	if (xec > 0x5)
844
		goto wrong_mc6_mce;
845

846
	pr_cont("%s parity error.\n", mc6_mce_desc[xec]);
847 848
	return;

849 850
 wrong_mc6_mce:
	pr_emerg(HW_ERR "Corrupted MC6 MCE info?\n");
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}

853
/* Decode errors according to Scalable MCA specification */
854
static void decode_smca_error(struct mce *m)
855
{
856
	struct smca_hwid *hwid;
857
	enum smca_bank_types bank_type;
858
	const char *ip_name;
859
	u8 xec = XEC(m->status, xec_mask);
860

861
	if (m->bank >= ARRAY_SIZE(smca_banks))
862 863
		return;

864 865
	hwid = smca_banks[m->bank].hwid;
	if (!hwid)
866 867
		return;

868
	bank_type = hwid->bank_type;
869 870 871 872 873 874

	if (bank_type == SMCA_RESERVED) {
		pr_emerg(HW_ERR "Bank %d is reserved.\n", m->bank);
		return;
	}

875
	ip_name = smca_get_long_name(bank_type);
876

877
	pr_emerg(HW_ERR "%s Extended Error Code: %d\n", ip_name, xec);
878

879 880
	/* Only print the decode of valid error codes */
	if (xec < smca_mce_descs[bank_type].num_descs &&
881
			(hwid->xec_bitmap & BIT_ULL(xec))) {
882 883 884
		pr_emerg(HW_ERR "%s Error: ", ip_name);
		pr_cont("%s.\n", smca_mce_descs[bank_type].descs[xec]);
	}
885 886

	if (bank_type == SMCA_UMC && xec == 0 && decode_dram_ecc)
887
		decode_dram_ecc(cpu_to_node(m->extcpu), m);
888 889
}

890
static inline void amd_decode_err_code(u16 ec)
891
{
892 893 894 895
	if (INT_ERROR(ec)) {
		pr_emerg(HW_ERR "internal: %s\n", UU_MSG(ec));
		return;
	}
896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911

	pr_emerg(HW_ERR "cache level: %s", LL_MSG(ec));

	if (BUS_ERROR(ec))
		pr_cont(", mem/io: %s", II_MSG(ec));
	else
		pr_cont(", tx: %s", TT_MSG(ec));

	if (MEM_ERROR(ec) || BUS_ERROR(ec)) {
		pr_cont(", mem-tx: %s", R4_MSG(ec));

		if (BUS_ERROR(ec))
			pr_cont(", part-proc: %s (%s)", PP_MSG(ec), TO_MSG(ec));
	}

	pr_cont("\n");
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}

914 915 916 917 918 919 920 921
/*
 * Filter out unwanted MCE signatures here.
 */
static bool amd_filter_mce(struct mce *m)
{
	/*
	 * NB GART TLB error reporting is disabled by default.
	 */
922
	if (m->bank == 4 && XEC(m->status, 0x1f) == 0x5 && !report_gart_errors)
923 924 925 926 927
		return true;

	return false;
}

928 929 930 931 932 933 934 935 936 937 938
static const char *decode_error_status(struct mce *m)
{
	if (m->status & MCI_STATUS_UC) {
		if (m->status & MCI_STATUS_PCC)
			return "System Fatal error.";
		if (m->mcgstatus & MCG_STATUS_RIPV)
			return "Uncorrected, software restartable error.";
		return "Uncorrected, software containable error.";
	}

	if (m->status & MCI_STATUS_DEFERRED)
939
		return "Deferred error, no action required.";
940 941 942 943

	return "Corrected error, no action required.";
}

944 945
static int
amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
946
{
947
	struct mce *m = (struct mce *)data;
948
	unsigned int fam = x86_family(m->cpuid);
949
	int ecc;
950

951 952 953
	if (amd_filter_mce(m))
		return NOTIFY_STOP;

954 955 956 957
	pr_emerg(HW_ERR "%s\n", decode_error_status(m));

	pr_emerg(HW_ERR "CPU:%d (%x:%x:%x) MC%d_STATUS[%s|%s|%s|%s|%s",
		m->extcpu,
958
		fam, x86_model(m->cpuid), x86_stepping(m->cpuid),
959 960
		m->bank,
		((m->status & MCI_STATUS_OVER)	? "Over"  : "-"),
961 962
		((m->status & MCI_STATUS_UC)	? "UE"	  :
		 (m->status & MCI_STATUS_DEFERRED) ? "-"  : "CE"),
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		((m->status & MCI_STATUS_MISCV)	? "MiscV" : "-"),
		((m->status & MCI_STATUS_PCC)	? "PCC"	  : "-"),
		((m->status & MCI_STATUS_ADDRV)	? "AddrV" : "-"));

967
	if (fam >= 0x15) {
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		pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-"));

		/* F15h, bank4, bit 43 is part of McaStatSubCache. */
971
		if (fam != 0x15 || m->bank != 4)
972 973
			pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-"));
	}
974

975
	if (boot_cpu_has(X86_FEATURE_SMCA)) {
976 977 978
		u32 low, high;
		u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);

979 980
		pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));

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		if (!rdmsr_safe(addr, &low, &high) &&
		    (low & MCI_CONFIG_MCAX))
			pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));
	}

986 987 988 989 990 991 992 993
	/* do the two bits[14:13] together */
	ecc = (m->status >> 45) & 0x3;
	if (ecc)
		pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));

	pr_cont("]: 0x%016llx\n", m->status);

	if (m->status & MCI_STATUS_ADDRV)
994
		pr_emerg(HW_ERR "Error Addr: 0x%016llx\n", m->addr);
995

996
	if (boot_cpu_has(X86_FEATURE_SMCA)) {
997 998
		pr_emerg(HW_ERR "IPID: 0x%016llx", m->ipid);

999 1000 1001 1002 1003
		if (m->status & MCI_STATUS_SYNDV)
			pr_cont(", Syndrome: 0x%016llx", m->synd);

		pr_cont("\n");

1004
		decode_smca_error(m);
1005
		goto err_code;
1006
	}
1007

1008 1009 1010
	if (m->tsc)
		pr_emerg(HW_ERR "TSC: %llu\n", m->tsc);

1011 1012 1013
	if (!fam_ops)
		goto err_code;

1014 1015
	switch (m->bank) {
	case 0:
1016
		decode_mc0_mce(m);
1017
		break;
1018

1019
	case 1:
1020
		decode_mc1_mce(m);
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		break;

1023
	case 2:
1024
		decode_mc2_mce(m);
1025 1026
		break;

1027
	case 3:
1028
		decode_mc3_mce(m);
1029 1030
		break;

1031
	case 4:
1032
		decode_mc4_mce(m);
1033 1034
		break;

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1035
	case 5:
1036
		decode_mc5_mce(m);
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1037 1038
		break;

1039
	case 6:
1040
		decode_mc6_mce(m);
1041 1042
		break;

1043 1044
	default:
		break;
1045
	}
1046

1047
 err_code:
1048
	amd_decode_err_code(m->status & 0xffff);
1049 1050

	return NOTIFY_STOP;
1051
}
1052

1053 1054
static struct notifier_block amd_mce_dec_nb = {
	.notifier_call	= amd_decode_mce,
1055
	.priority	= MCE_PRIO_EDAC,
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};

1058 1059
static int __init mce_amd_init(void)
{
1060 1061
	struct cpuinfo_x86 *c = &boot_cpu_data;

1062 1063
	if (c->x86_vendor != X86_VENDOR_AMD &&
	    c->x86_vendor != X86_VENDOR_HYGON)
1064
		return -ENODEV;
1065

1066 1067 1068 1069
	fam_ops = kzalloc(sizeof(struct amd_decoder_ops), GFP_KERNEL);
	if (!fam_ops)
		return -ENOMEM;

1070
	switch (c->x86) {
1071
	case 0xf:
1072 1073
		fam_ops->mc0_mce = k8_mc0_mce;
		fam_ops->mc1_mce = k8_mc1_mce;
1074
		fam_ops->mc2_mce = k8_mc2_mce;
1075 1076 1077
		break;

	case 0x10:
1078 1079
		fam_ops->mc0_mce = f10h_mc0_mce;
		fam_ops->mc1_mce = k8_mc1_mce;
1080
		fam_ops->mc2_mce = k8_mc2_mce;
1081 1082
		break;

1083
	case 0x11:
1084 1085
		fam_ops->mc0_mce = k8_mc0_mce;
		fam_ops->mc1_mce = k8_mc1_mce;
1086
		fam_ops->mc2_mce = k8_mc2_mce;
1087 1088
		break;

1089
	case 0x12:
1090 1091
		fam_ops->mc0_mce = f12h_mc0_mce;
		fam_ops->mc1_mce = k8_mc1_mce;
1092
		fam_ops->mc2_mce = k8_mc2_mce;
1093 1094
		break;