clk-mux.c 5.8 KB
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// SPDX-License-Identifier: GPL-2.0
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/*
 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
 *
 * Simple multiplexer clock implementation
 */

#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>

/*
 * DOC: basic adjustable multiplexer clock that cannot gate
 *
 * Traits of this clock:
 * prepare - clk_prepare only ensures that parents are prepared
 * enable - clk_enable only ensures that parents are enabled
 * rate - rate is only affected by parent switching.  No clk_set_rate support
 * parent - parent is adjustable through clk_set_parent
 */

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int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
			 unsigned int val)
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{
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	int num_parents = clk_hw_get_num_parents(hw);
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	if (table) {
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		int i;

		for (i = 0; i < num_parents; i++)
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			if (table[i] == val)
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				return i;
		return -EINVAL;
	}
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	if (val && (flags & CLK_MUX_INDEX_BIT))
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		val = ffs(val) - 1;

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	if (val && (flags & CLK_MUX_INDEX_ONE))
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		val--;

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	if (val >= num_parents)
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		return -EINVAL;

	return val;
}
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EXPORT_SYMBOL_GPL(clk_mux_val_to_index);
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unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
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{
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	unsigned int val = index;
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	if (table) {
		val = table[index];
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	} else {
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		if (flags & CLK_MUX_INDEX_BIT)
			val = 1 << index;
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		if (flags & CLK_MUX_INDEX_ONE)
			val++;
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	}
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	return val;
}
EXPORT_SYMBOL_GPL(clk_mux_index_to_val);

static u8 clk_mux_get_parent(struct clk_hw *hw)
{
	struct clk_mux *mux = to_clk_mux(hw);
	u32 val;

	val = clk_readl(mux->reg) >> mux->shift;
	val &= mux->mask;

	return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
}

static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
	struct clk_mux *mux = to_clk_mux(hw);
	u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
	unsigned long flags = 0;
	u32 reg;

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	if (mux->lock)
		spin_lock_irqsave(mux->lock, flags);
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	else
		__acquire(mux->lock);
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	if (mux->flags & CLK_MUX_HIWORD_MASK) {
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		reg = mux->mask << (mux->shift + 16);
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	} else {
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		reg = clk_readl(mux->reg);
		reg &= ~(mux->mask << mux->shift);
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	}
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	val = val << mux->shift;
	reg |= val;
	clk_writel(reg, mux->reg);
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	if (mux->lock)
		spin_unlock_irqrestore(mux->lock, flags);
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	else
		__release(mux->lock);
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	return 0;
}

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static int clk_mux_determine_rate(struct clk_hw *hw,
				  struct clk_rate_request *req)
{
	struct clk_mux *mux = to_clk_mux(hw);

	return clk_mux_determine_rate_flags(hw, req, mux->flags);
}

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const struct clk_ops clk_mux_ops = {
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	.get_parent = clk_mux_get_parent,
	.set_parent = clk_mux_set_parent,
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	.determine_rate = clk_mux_determine_rate,
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};
EXPORT_SYMBOL_GPL(clk_mux_ops);

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const struct clk_ops clk_mux_ro_ops = {
	.get_parent = clk_mux_get_parent,
};
EXPORT_SYMBOL_GPL(clk_mux_ro_ops);

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struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
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		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
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		void __iomem *reg, u8 shift, u32 mask,
		u8 clk_mux_flags, u32 *table, spinlock_t *lock)
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{
	struct clk_mux *mux;
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	struct clk_hw *hw;
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	struct clk_init_data init;
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	u8 width = 0;
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	int ret;
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	if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
		width = fls(mask) - ffs(mask) + 1;
		if (width + shift > 16) {
			pr_err("mux value exceeds LOWORD field\n");
			return ERR_PTR(-EINVAL);
		}
	}
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	/* allocate the mux */
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	mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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	if (!mux)
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		return ERR_PTR(-ENOMEM);

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	init.name = name;
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	if (clk_mux_flags & CLK_MUX_READ_ONLY)
		init.ops = &clk_mux_ro_ops;
	else
		init.ops = &clk_mux_ops;
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	init.flags = flags | CLK_IS_BASIC;
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	init.parent_names = parent_names;
	init.num_parents = num_parents;

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	/* struct clk_mux assignments */
	mux->reg = reg;
	mux->shift = shift;
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	mux->mask = mask;
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	mux->flags = clk_mux_flags;
	mux->lock = lock;
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	mux->table = table;
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	mux->hw.init = &init;
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	hw = &mux->hw;
	ret = clk_hw_register(dev, hw);
	if (ret) {
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		kfree(mux);
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		hw = ERR_PTR(ret);
	}
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	return hw;
}
EXPORT_SYMBOL_GPL(clk_hw_register_mux_table);

struct clk *clk_register_mux_table(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
		void __iomem *reg, u8 shift, u32 mask,
		u8 clk_mux_flags, u32 *table, spinlock_t *lock)
{
	struct clk_hw *hw;

	hw = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
				       flags, reg, shift, mask, clk_mux_flags,
				       table, lock);
	if (IS_ERR(hw))
		return ERR_CAST(hw);
	return hw->clk;
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}
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EXPORT_SYMBOL_GPL(clk_register_mux_table);
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struct clk *clk_register_mux(struct device *dev, const char *name,
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		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
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		void __iomem *reg, u8 shift, u8 width,
		u8 clk_mux_flags, spinlock_t *lock)
{
	u32 mask = BIT(width) - 1;

	return clk_register_mux_table(dev, name, parent_names, num_parents,
				      flags, reg, shift, mask, clk_mux_flags,
				      NULL, lock);
}
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EXPORT_SYMBOL_GPL(clk_register_mux);
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struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
		const char * const *parent_names, u8 num_parents,
		unsigned long flags,
		void __iomem *reg, u8 shift, u8 width,
		u8 clk_mux_flags, spinlock_t *lock)
{
	u32 mask = BIT(width) - 1;

	return clk_hw_register_mux_table(dev, name, parent_names, num_parents,
				      flags, reg, shift, mask, clk_mux_flags,
				      NULL, lock);
}
EXPORT_SYMBOL_GPL(clk_hw_register_mux);

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void clk_unregister_mux(struct clk *clk)
{
	struct clk_mux *mux;
	struct clk_hw *hw;

	hw = __clk_get_hw(clk);
	if (!hw)
		return;

	mux = to_clk_mux(hw);

	clk_unregister(clk);
	kfree(mux);
}
EXPORT_SYMBOL_GPL(clk_unregister_mux);
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void clk_hw_unregister_mux(struct clk_hw *hw)
{
	struct clk_mux *mux;

	mux = to_clk_mux(hw);

	clk_hw_unregister(hw);
	kfree(mux);
}
EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);